Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Energy Saving Testing of Circuits
Automation and Remote Control
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
Screening for Known Good Die (KGD) Based on Defect Clustering: An Experimental Study
Proceedings of the IEEE International Test Conference
An analysis of power reduction techniques in scan testing
Proceedings of the IEEE International Test Conference 2001
A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Delta Iddq for Testing Reliability
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Scan-Based Testing: The Only Practical Solution for Testing ASIC/Consumer Products
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Wafer-Package Test Mix for Optimal Defect Detection and Test Time Savings
IEEE Design & Test
The Cross Entropy Method: A Unified Approach To Combinatorial Optimization, Monte-carlo Simulation (Information Science and Statistics)
On Low-Capture-Power Test Generation for Scan Testing
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
ITC '04 Proceedings of the International Test Conference on International Test Conference
Enhancing Delay Fault Coverage through Low Power Segmented Scan
ETS '06 Proceedings of the Eleventh IEEE European Test Symposium
ATPG for Dynamic Burn-In Test in Full-Scan Circuits
ATS '06 Proceedings of the 15th Asian Test Symposium
Scan test planning for power reduction
Proceedings of the 44th annual Design Automation Conference
Power Management for Wafer-Level Test During Burn-In
ATS '08 Proceedings of the 2008 17th Asian Test Symposium
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An automatic test pattern generator for minimizing switching activity during scan testing activity
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On Gilmore-Gomory's open question for the bottleneck TSP
Operations Research Letters
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Wafer-level test during burn-in (WLTBI) is a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, scan-based testing leads to significant power variations in a die during test-pattern application. This variation adversely affects the accuracy of predictions of junction temperatures and the time required for burn-in. We present a test-pattern ordering technique for WLTBI, where the objective is to minimize the variation in power consumption during test application. The test-pattern ordering problem for WLTBI is formulated and solved optimally using integer linear programming. Efficient heuristic methods are also presented to easily solve the pattern-ordering problem for large circuits. Simulation results are presented for the ISCAS'89 and the IWLS'05 benchmark circuits, and the proposed ordering technique is compared with two baseline methods that carry out pattern ordering to minimize peak power and average power, respectively. A third baseline method that randomly orders test patterns is also used to evaluate the proposed methods.