Power management using test-pattern ordering for wafer-level test during burn-in
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Wafer-level test during burn-in (WLTBI) has recently emerged as a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, test during burn-in can lead to significant power variations in the die. This variation adversely affects the accuracy of predictions of junction temperatures and the time required for burn-in. We present a test-pattern manipulation technique for WLTBI, where the objective is to minimize the variation in power consumption during test application. Test-pattern manipulation is carried out by carefully filling the don't-care bits in test cubes. The $X$-fill problem is formulated and solved using an efficient polynomial-time algorithm. Simulation results are presented for the ISCAS'89 and the IWLS'05 benchmark circuits, and the proposed technique is compared with three baseline methods that carry out pattern manipulation to minimize peak-power consumption.