Reduction of Power and Test Time by Removing Cluster of Don't-Care from Test Data Set
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Two efficient methods to reduce power and testing time
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Power management using test-pattern ordering for wafer-level test during burn-in
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper describes a echnique for re-ordering ofscan cells to minimize power dissipation that is alsocapable of reducing the area overhead of the circuitcompared to a random ordering of the scan cells. For agiven test set, our proposed greedy algorithm finds the(locally) optimal scan cell ordering for a given value of \lambda,which is a rade-off parameter hat can be used by hedesigner to specify the relative importance of areaoverhead minimization and power minimization. Thestrength of our algorithm lies in the fact that we use anovel dynamic minimum transition fill (MT-fill) techniqueto fill the unspecified bits in the test vector. Experimentsperformed on the ISCAS-89 benchmark suite show areduction in power (70%for s13207, \lambda = 500) as well asa reduction in layout area (6.72%for s13207, \lambda = 500).