A layout-based approach for ordering scan chain flip-flops
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Reduction of power dissipation and test time is accomplished by forming two clusters of donýt-care inside an input and a response test cube, respectively. These clusters are out of the scan operation.