Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Optimal Configuring of Multiple Scan Chains
IEEE Transactions on Computers
Scan chain design for test time reduction in core-based ICs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A layout-based approach for ordering scan chain flip-flops
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A novel scan architecture for power-efficient, rapid test
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Reducing Test Application Time for Full Scan Embedded Cores
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
A Modified Clock Scheme for a Low Power BIST Test Pattern Generator
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Reducing Power Dissipation during Test Using Scan Chain Disable
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
The Efficient Multiple Scan Chain Architecture Reducing Power Dissipation and Test Time
ATS '04 Proceedings of the 13th Asian Test Symposium
A selective pattern-compression scheme for power and test-data reduction
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
On reducing test power and test volume by selective pattern compression schemes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
Reducing power dissipation and testing time is accomplished by forming two clusters of don't-care bit inside an input and a response test cube. New reordering scheme of scan latches is proposed to create the clusters of don't-care bit, and two proposed reconfigured scan architecture guarantee to remove the clusters from the scan operation. The size of these clusters is directly proportional to the amount of power and testing time that is reduced. Results with ISCAS'89 benchmark circuits show good improvement in both power consumption and test time