Using the Nonlinear Property of FSR and Dictionary Coding for Reduction of Test Volume
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Two efficient methods to reduce power and testing time
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scan-chain design and optimization for three-dimensional integrated circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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The efficient use of unspecified bit in input test cube and its response test cube (henceforth, test set) reduces power dissipation and test time in the multiple scan chain architecture. First, unspecified bits in test set are clustered by reordering scan latches, and then the multiple scan chain architecture is modified by inserting multiplexers (MUXes) in each scan chain in order to implement the reordering for reduction of power and test time. Results with ISCASý89 benchmark circuits show a good improvement in both power dissipation and test time.