Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Reduction of SOC test data volume, scan power and testing time using alternating run-length codes
Proceedings of the 39th annual Design Automation Conference
Test vector encoding using partial LFSR reseeding
Proceedings of the IEEE International Test Conference 2001
Scan Vector Compression/Decompression Using Statistical Coding
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Test Data Compression Using Dictionaries with Fixed-Length Indices
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
BIST RESEEDING WITH VERY FEW SEEDS
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Combining dictionary coding and LFSR reseeding for test data compression
Proceedings of the 41st annual Design Automation Conference
The Efficient Multiple Scan Chain Architecture Reducing Power Dissipation and Test Time
ATS '04 Proceedings of the 13th Asian Test Symposium
Test set compaction algorithms for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Using the nonlinear feedback shift register in testing is known to create a test set for combinational circuits instead of using the deterministic test set. The nonlinear property of feedback shift register is used differently here to reduce the test data volume for combinational circuits without using the nonlinear feedback shift register. In addition, a dictionary coding method is applied to further decrease a reduced test set. Results with benchmark circuits show a great improvement in the reduction of test data volume.