IEEE Transactions on Computers - Special issue on fault-tolerant computing
ATPG for heat dissipation minimization during scan testing
DAC '97 Proceedings of the 34th annual Design Automation Conference
Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Combining low-power scan testing and test data compression for system-on-a-chip
Proceedings of the 38th annual Design Automation Conference
A case study on the implementation of the Illinois Scan Architecture
Proceedings of the IEEE International Test Conference 2001
Scan array solution for testing power and testing time
Proceedings of the IEEE International Test Conference 2001
Test vector decompression via cyclical scan chains and its application to testing core-based designs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An analysis of power reduction techniques in scan testing
Proceedings of the IEEE International Test Conference 2001
Reducing Test Application Time for Full Scan Embedded Cores
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A Test Vector Inhibiting Technique for Low Energy BIST Design
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Low Power BIST via Non-Linear Hybrid Cellular Automata
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
A Modified Clock Scheme for a Low Power BIST Test Pattern Generator
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test scheduling for core-based systems using mixed-integer linear programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-on-a-chip test-data compression and decompression architectures based on Golomb codes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Technique for High Ratio LZW Compression
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
RL-huffman encoding for test compression and power reduction in scan applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On Reducing Peak Current and Power during Test
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Using the Nonlinear Property of FSR and Dictionary Coding for Reduction of Test Volume
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
A Huffman-based coding with efficient test application
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
New test data decompressor for low power applications
Proceedings of the 44th annual Design Automation Conference
Test data compression scheme based on variable-to-fixed-plus-variable-length coding
Journal of Systems Architecture: the EUROMICRO Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing
Journal of Electronic Testing: Theory and Applications
An Effective Power Reduction Methodology for Deterministic BIST Using Auxiliary LFSR
Journal of Electronic Testing: Theory and Applications
On capture power-aware test data compression for scan-based testing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A Variable-Length Coding Adjustable for Compressed Test Application
IEICE - Transactions on Information and Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Low-power scan operation in test compression environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal of Electronic Testing: Theory and Applications
Reducing the switching activity of test sequences under transparent-scan
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimization of Test Power and Data Volume in BIST Scheme Based on Scan Slice Overlapping
Journal of Electronic Testing: Theory and Applications
Capture-power-aware test data compression using selective encoding
Integration, the VLSI Journal
A new scheme of test data compression based on equal-run-length coding (ERLC)
Integration, the VLSI Journal
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
A modified scheme for simultaneous reduction of test data volume and testing power
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Low-power skewed-load tests based on functional broadside tests
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-power test sets under test-related primary input constraints
International Journal of Critical Computer-Based Systems
| Hi-index | 0.00 |
We present a test resource partitioning (TRP) technique that simultaneously reduces test data volume, test application time and scan power. The proposed approach is based on the use of alternating run-length codes for test data compression. Experimental results for the larger ISCAS-89 benchmarks and an IBM production circuit show that reduced test data volume, test application time and low power scan testing can indeed be achieved in all cases.