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An analysis of power reduction techniques in scan testing
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Peak-power reduction for multiple-scan circuits during test application
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Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
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Test Vector Modification for Power Reduction during Scan Testing
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On test generation for transition faults with minimized peak power dissipation
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Test Power Reduction with Multiple Capture Orders
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Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
ITC '04 Proceedings of the International Test Conference on International Test Conference
DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs
IEEE Transactions on Computers
Interactive presentation: On power-profiling and pattern generation for power-safe scan tests
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LS-TDF: Low-Switching Transition Delay Fault Pattern Generation
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
A Capture-Safe Test Generation Scheme for At-Speed Scan Testing
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improved weight assignment for logic switching activity during at-speed test pattern generation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Augmenting Functional Broadside Tests for Transition Fault Coverage with Bounded Switching Activity
PRDC '11 Proceedings of the 2011 IEEE 17th Pacific Rim International Symposium on Dependable Computing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Forward-looking fault simulation for improved static compaction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper considers the generation of low-power test sets under test-related primary input constraints. Such constraints are used for addressing tester limitations related to the application of tests at-speed. Specifically, the paper considers the switching activity which measures the power dissipation during the fast functional clock cycles of broadside tests with constrained primary input vectors. For a functional broadside test, the switching activity during the fast functional clock cycle is guaranteed not to exceed the switching activity possible during functional operation. Therefore, functional broadside tests are appropriate as low-power tests. In addition, the switching activity of functional broadside tests can be used for bounding the switching activity of other tests in a low-power test set. The paper observes that functional broadside tests for computing the bound should be generated under the same primary input constraint as the low-power test set. This is important since primary input constraints affect the switching activity possible in parts of the circuit that are influenced by the primary inputs. It helps ensure that the switching activity in other parts of the circuit will not be higher, or not be restricted to be lower, than during functional operation.