On Reducing Peak Current and Power during Test
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
A selective pattern-compression scheme for power and test-data reduction
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Journal of Electronic Testing: Theory and Applications
QC-fill: quick-and-cool X-filling for multicasting-based scan test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
QC-fill: an X-fill method for quick-and-cool scan test
Proceedings of the Conference on Design, Automation and Test in Europe
X-filling for simultaneous shift- and capture-power reduction in at-speed scan-based testing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reducing the switching activity of test sequences under transparent-scan
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On reducing test power and test volume by selective pattern compression schemes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MVP: capture-power reduction with minimum-violations partitioning for delay testing
Proceedings of the International Conference on Computer-Aided Design
Low-power skewed-load tests based on functional broadside tests
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design-for-testability for multi-cycle broadside tests by holding of state variables
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-power test sets under test-related primary input constraints
International Journal of Critical Computer-Based Systems
Observation-Oriented ATPG and Scan Chain Disabling for Capture Power Reduction
Journal of Electronic Testing: Theory and Applications
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This paper proposes a novel method to reduce the excess power dissipation during scan testing. The proposed method divides a scan chain into a number of sub-chains, and enables only one sub-chain at a time for both the scan and capture operations. To efficiently deal with the data dependence problem during the capture cycles, we develop a multiple-capture-orders method to guarantee the full scan fault coverage. A novel test pattern generation procedure is developed to reduce the test application time and a test architecture based on a ring control structure is adopted which makes the test control very simple and requires very low area overhead. Experimental results for large ISCASý89 benchmark circuits show that the proposed method can reduce average and peak power by 86.8% and 66.1% in average, respectively, when 8 sub-chains are used.