On static compaction of test sequences for synchronous sequential circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Reduction of SOC test data volume, scan power and testing time using alternating run-length codes
Proceedings of the 39th annual Design Automation Conference
Scan Architecture for Shift and Capture Cycle Power Reduction
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
An analysis of power reduction techniques in scan testing
Proceedings of the IEEE International Test Conference 2001
Proceedings of the IEEE International Test Conference 2001
Proceedings of the 40th annual Design Automation Conference
Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption
ATS '99 Proceedings of the 8th Asian Test Symposium
Peak-power reduction for multiple-scan circuits during test application
ATS '00 Proceedings of the 9th Asian Test Symposium
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Vector Modification for Power Reduction during Scan Testing
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Test Application Time Reduction for Scan Circuits Using Limited Scan Operations
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
On test generation for transition faults with minimized peak power dissipation
Proceedings of the 41st annual Design Automation Conference
A New Approach to Test Generation and Test Compaction for Scan Circuits
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Test Power Reduction with Multiple Capture Orders
ATS '04 Proceedings of the 13th Asian Test Symposium
On Reducing Peak Current and Power during Test
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
ITC '04 Proceedings of the International Test Conference on International Test Conference
Test compaction for transition faults under transparent-scan
Proceedings of the conference on Design, automation and test in Europe: Proceedings
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Transparent-scan is a test application scheme for scan circuits. It provides unique opportunities for test compaction that do not exist with the standard test application scheme. We show that it also provides unique opportunities for reducing the power dissipation of a scan-based test set. After translating a standard scan-based test set into a transparent-scan sequence, we apply two operations for reducing the power dissipation of the sequence. The first operation attempts to remove a test vector that causes high power dissipation. The second operation attempts to replace a scan clock cycle with a functional clock cycle, or a functional clock cycle with a scan clock cycle, in order to reduce the power dissipation. Both operations are implemented such that they reduce the power dissipation without reducing the fault coverage. We also consider a third operation that attempts to complement arbitrary values in the transparent-scan sequence in order to further reduce the power dissipation.