On Reducing Peak Current and Power during Test
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Low power Illinois scan architecture for simultaneous power and test data volume reduction
Proceedings of the conference on Design, automation and test in Europe
Reducing the switching activity of test sequences under transparent-scan
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-power scan design using first-level supply gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Observation-Oriented ATPG and Scan Chain Disabling for Capture Power Reduction
Journal of Electronic Testing: Theory and Applications
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Low power design techniques have been employed for more than two decades, however anemerging problem is satisfying the test power constraints for avoiding destructive test and improving the yield. Scan architectures represent the most used approach for testing digital integrated circuits. While several methods have been proposed for reducing the power dissipation due to scan shifting, very little work has been done towards reducing the power dissipation during the capture cycles. This paper proposes a method of transforming a typical scan architecture for reducing the power dissipation during both the shifting cycle and the capture cycle. The basic idea is to split the the scan chain into multiple length-balanced partitions and to enable only one partition at each test clock. This way, instead of having all the scan cells active at the same time, only a fraction of them will be active in each test clock cycle, which will reduce substantially the power dissipation in the circuit under test. Unlike previously proposed methods for shifting power reduction based on scan chain partitioning [7-10] which use a single capture clock per test cycle, our approach uses multiple capture clocks per test cycle, which allows enabling only a fraction of the scan chain during each shift or capture clock, thus reducing the switching activity in the circuit under test not only during shifting but also during capture. Therefore, the proposed method represents an unified solution for reducing both shifting and capture power dissipation during scan-based test. The proposed method also allows full reuse of the test vectors of the original scan architecture.