Reduction of SOC test data volume, scan power and testing time using alternating run-length codes
Proceedings of the 39th annual Design Automation Conference
IEEE Transactions on Computers
Design of Routing-Constrained Low Power Scan Chains
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Power-Driven Routing-Constrained Scan Chain Design
Journal of Electronic Testing: Theory and Applications
Power-Aware Test Planning in the Early System-on-Chip Design Exploration Process
IEEE Transactions on Computers
A Gated Clock Scheme for Low Power Testing of Logic Cores
Journal of Electronic Testing: Theory and Applications
A critical-path-aware partial gating approach for test power reduction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
New test data decompressor for low power applications
Proceedings of the 44th annual Design Automation Conference
Securing Designs against Scan-Based Side-Channel Attacks
IEEE Transactions on Dependable and Secure Computing
Low power Illinois scan architecture for simultaneous power and test data volume reduction
Proceedings of the conference on Design, automation and test in Europe
CASP: concurrent autonomous chip self-test using stored test patterns
Proceedings of the conference on Design, automation and test in Europe
A Reconfigurable Power Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling
Journal of Electronic Testing: Theory and Applications
Efficient partial scan cell gating for low-power scan-based testing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A New Scan Power Reduction Scheme Using Transition Freezing for Pseudo-Random Logic BIST
IEICE - Transactions on Information and Systems
A power-effective scan architecture using scan flip-flops clustering and post-generation filling
Proceedings of the 19th ACM Great Lakes symposium on VLSI
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A test set embedding approach based on twisted-ring counter with few seeds
Integration, the VLSI Journal
LPTest: a Flexible Low-Power Test Pattern Generator
Journal of Electronic Testing: Theory and Applications
Low-power scan operation in test compression environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
QC-fill: quick-and-cool X-filling for multicasting-based scan test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power management using test-pattern ordering for wafer-level test during burn-in
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scan-Cell Reordering for Minimizing Scan-Shift Power Based on Nonspecified Test Cubes
ACM Transactions on Design Automation of Electronic Systems (TODAES)
QC-fill: an X-fill method for quick-and-cool scan test
Proceedings of the Conference on Design, Automation and Test in Europe
Reducing the switching activity of test sequences under transparent-scan
ACM Transactions on Design Automation of Electronic Systems (TODAES)
SOC test planning using virtual test access architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Controlling peak power consumption during scan testing: power-aware DfT and test set perspectives
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Low-power skewed-load tests based on functional broadside tests
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-power test sets under test-related primary input constraints
International Journal of Critical Computer-Based Systems
Observation-Oriented ATPG and Scan Chain Disabling for Capture Power Reduction
Journal of Electronic Testing: Theory and Applications
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