Combining low-power scan testing and test data compression for system-on-a-chip
Proceedings of the 38th annual Design Automation Conference
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
An analysis of power reduction techniques in scan testing
Proceedings of the IEEE International Test Conference 2001
Peak-power reduction for multiple-scan circuits during test application
ATS '00 Proceedings of the 9th Asian Test Symposium
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores
ATS '01 Proceedings of the 10th Asian Test Symposium
Reducing Power Dissipation during Test Using Scan Chain Disable
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Controlling Peak Power During Scan Testing
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Test Power Reduction with Multiple Capture Orders
ATS '04 Proceedings of the 13th Asian Test Symposium
On Low-Capture-Power Test Generation for Scan Testing
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
ITC '04 Proceedings of the International Test Conference on International Test Conference
ATS '06 Proceedings of the 15th Asian Test Symposium
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
Low Power Embedded Deterministic Test
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
New test data decompressor for low power applications
Proceedings of the 44th annual Design Automation Conference
Response Inversion Scan Cell (RISC): A Peak Capture Power Reduction Technique
ATS '07 Proceedings of the 16th Asian Test Symposium
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting
IEEE Design & Test
Low power Illinois scan architecture for simultaneous power and test data volume reduction
Proceedings of the conference on Design, automation and test in Europe
A unified approach to reduce SOC test data volume, scan power and testing time
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2009 International Conference on Computer-Aided Design
QC-fill: quick-and-cool X-filling for multicasting-based scan test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal of Electronic Testing: Theory and Applications
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In this paper, we present an X-Fill (QC-Fill) method for not only slashing the test time but also reducing the test power (including both capture power and shifting power). QC-Fill, built upon the existing multicasting scan architecture, can coexist with most low-capture-power (LCP) X-fill methods through a multicasting-driven X-fill method incorporating a clique-stripping scheme. QC-Fill is independent of the ATPG patterns and does not require any area-overhead since it can directly operate on an existing scan architecture incorporating test compression.