Low Power Embedded Deterministic Test

Authors:
Dariusz Czysz;Grzegorz Mrugalski;Janusz Rajski;Jerzy Tyszer
Affiliations:
Poznan University of Technology, Poland;Mentor Graphics Corporation, USA;Mentor Graphics Corporation, USA;Poznan University of Technology, Poland
Venue:
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Year:
2007

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Abstract

This paper presents a novel low power test scheme integrated with the embedded deterministic test environment. It reduces switching rates in scan chains with no hardware modification. Experimental results obtained for industrial circuits indicate that switching activity can be reduced up to 23 times.