Test vector encoding using partial LFSR reseeding
Proceedings of the IEEE International Test Conference 2001
MD-SCAN Method for Low Power Scan Testing
ATS '02 Proceedings of the 11th Asian Test Symposium
20.3 A Test Pattern Generation Methodology for Low-Power Consumption
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-Seeding
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Low Power Test Data Compression Based on LFSR Reseeding
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
ITC '04 Proceedings of the International Test Conference on International Test Conference
A New ATPG Method for Efficient Capture Power Reduction During Scan Testing
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Survey of Test Vector Compression Techniques
IEEE Design & Test
Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects
ATS '06 Proceedings of the 15th Asian Test Symposium
Low Power Embedded Deterministic Test
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Supply Voltage Noise Aware ATPG for Transition Delay Faults
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
New test data decompressor for low power applications
Proceedings of the 44th annual Design Automation Conference
On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers
An Efficient Peak Power Reduction Technique for Scan Testing
ATS '07 Proceedings of the 16th Asian Test Symposium
A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Methodology for low power test pattern generation using activity threshold control logic
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
An automatic test pattern generator for minimizing switching activity during scan testing activity
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Ring generators - new devices for embedded test applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LFSR-Reseeding Scheme Achieving Low-Power Dissipation During Test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Yield loss caused by excessive power supply noise has become a serious problem in at-speed scan testing. Although X-filling techniques are available to reduce the launch cycle switching activity, their performance may not be satisfactory in the linear-decompressor-based test compression environment. This paper solves this problem by proposing a novel integrated automatic test pattern generation scheme that efficiently and effectively performs compressible low-capture-power X-filling. Related theoretical principles are established, based on which the problem size is substantially reduced. The proposed scheme is validated by benchmark circuits, as well as an industry design in the embedded deterministic test environment.