High Performance Dense Ring Generators
IEEE Transactions on Computers
Survey of Test Vector Compression Techniques
IEEE Design & Test
Power supply noise reduction for at-speed scan testing in linear-decompression environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High volume diagnosis in memory BIST based on compressed failure data
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Finding matching initial states for equivalent NLFSRs in the Fibonacci and the Galois configurations
IEEE Transactions on Information Theory
An algorithm for constructing a fastest Galois NLFSR generating a given sequence
SETA'10 Proceedings of the 6th international conference on Sequences and their applications
Time-multiplexed compressed test of SOC designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Capture-power-aware test data compression using selective encoding
Integration, the VLSI Journal
Synthesis of parallel binary machines
Proceedings of the International Conference on Computer-Aided Design
Test-data volume and scan-power reduction with low ATE interface for multi-core SoCs
Proceedings of the International Conference on Computer-Aided Design
Efficient Test Compression Technique for SoC Based on Block Merging and Eight Coding
Journal of Electronic Testing: Theory and Applications
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This paper presents a novel methodology of designing generators and compactors of test data. The essence of the proposed approach is to use a set of transformations, which alters the structure of the conventional linear feedback shift registers (LFSRs) while preserving the transition function of the original circuits. It is shown that after applying the transition function preserving transformations in a certain order, the resultant circuits feature a significantly reduced the number of levels of XOR logic, minimized internal fanouts, and simplified circuit layout and routing, as compared to previous schemes based on external feedback LFSRs, internal feedback LFSRs, and cellular automata, all implementing the same characteristic polynomial. Consequently, the proposed devices can operate at higher speeds than those of conventional solutions and become highly modular structures.