High volume diagnosis in memory BIST based on compressed failure data

Authors:
Nilanjan Mukherjee;Artur Pogiel;Janusz Rajski;Jerzy Tyszer
Affiliations:
Mentor Graphics Corporation, Wilsonville, OR;Mentor Graphics Polska, Poznañ, Poland;Mentor Graphics Corporation, Wilsonville, OR;Faculty of Electronics and Telecommunications, Poznañ University of Technology, Poznañ, Poland
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2010

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Abstract

Embedded memories are increasingly identified as having potential for introducing new yield loss mechanisms at a rate, magnitude, and complexity large enough to demand major changes in fault diagnosis techniques. In particular, time-related or complex read faults that originate in the highest density areas of semiconductor designs require new methods to diagnose more complex faults affecting large groups of memory cells. This paper presents a built-in self-test (BIST)-based fault diagnosis scheme that can be used to identify a variety of failures in embedded random-access memory arrays. The proposed solution employs flexible test logic to record test responses at the system speed with no interruptions of a BIST session. It offers a simple test flow and enables detection of time-related faults. Furthermore, the way test responses are processed allows accurate and time-efficient reconstruction of error bitmaps. The proposed diagnostic algorithms use a number of techniques, including discrete logarithm-based counting with ring generators acting as very fast event counters and signature analyzers. Experimental results confirm high diagnostic accuracy of the proposed scheme and its time efficiency.