The method of parallel-sequential built-in self-testing in integrated circuits of the type SFPGAS
Automation and Remote Control
High volume diagnosis in memory BIST based on compressed failure data
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Control-ready architecture for self-testing in programmable logical matrix structures
Automation and Remote Control
X-compact: an efficient response compaction technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test Response Compaction via Output Bit Selection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Consideration was given to a controllable architecture enabling easy, simple and prompt self-testing in the programmable logic matrix. An approach was proposed to reduce the amount of self-testing hardware by compacting the test response by mod 2 convolution schemes through reconfiguration of the subject of diagnosis programmed in the matrix and using its standard connections.