Logic design principles with emphasis on testable semicustom circuits
Logic design principles with emphasis on testable semicustom circuits
Discrete logarithms in finite fields and their cryptographic significance
Proc. of the EUROCRYPT 84 workshop on Advances in cryptology: theory and application of cryptographic techniques
Measuring VAX 8800 performance with a histogram hardware monitor
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Performance from architecture: comparing a RISC and a CISC with similar hardware organization
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
The art of computer programming, volume 1 (3rd ed.): fundamental algorithms
The art of computer programming, volume 1 (3rd ed.): fundamental algorithms
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
Synthesis of Binary Ring Counters of Given Periods
Journal of the ACM (JACM)
Shift Register Sequences
A Characterization of Processor Performance in the vax-11/780
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
On-line sensing for healthier FPGA systems
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
High volume diagnosis in memory BIST based on compressed failure data
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-cost sensing with ring oscillator arrays for healthier reconfigurable systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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A linear feedback shift register, or LFSR, can implement an event counter by shifting whenever an event occurs. A single two-input exclusive-OR gate is often the only additional hardware necessary to allow a shift register to generate, by successive shifts, all of its possible nonzero values. The counting application requires that the number of shifts be recoverable from the LFSR contents so that further processing and analysis may be done. Recovering this number from the shift register value corresponds to a problem from number theory and cryptography known as the discrete logarithm. For some sizes of shift register, the maximal-length LFSR implementation requires more than a single gate, and for some, the discrete logarithm calculation is hard. The paper proposes for such size the use of certain one-gate LFSR's whose sequence lengths are nearly maximal, and which support easy discrete logarithms. These LFSR's have a concise mathematical characterization, and are quite common. The paper concludes by describing an application of these ideas in a computer hardware monitor, and by presenting a table that describes efficient LFSR's of size up to 64 bits.