Pseudorandom Bit Generators in Stream-Cipher Cryptography
Computer - Special issue on cryptography
Multiple-valued logic synthesis and optimization
Logic Synthesis and Verification
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Shift Register Sequences
High Speed Generation of Maximal Length Sequences
IEEE Transactions on Computers
New Stream Cipher Designs
A transformation from the Fibonacci to the Galois NLFSRs
IEEE Transactions on Information Theory
The maximum order complexity of sequence ensembles
EUROCRYPT'91 Proceedings of the 10th annual international conference on Theory and application of cryptographic techniques
Application of LFSRs for parallel sequence generation in cryptologic algorithms
ICCSA'06 Proceedings of the 2006 international conference on Computational Science and Its Applications - Volume Part III
Peak-to-mean power control in OFDM, Golay complementary sequences, and Reed-Muller codes
IEEE Transactions on Information Theory
Binary sequences with merit factor 6.3
IEEE Transactions on Information Theory
Results on the nonlinear span of binary sequences
IEEE Transactions on Information Theory
On the quadratic span of binary sequences
IEEE Transactions on Information Theory
On the Nonlinear Complexity and Lempel–Ziv Complexity of Finite Length Sequences
IEEE Transactions on Information Theory
Ring generators - new devices for embedded test applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RFID security and privacy: a research survey
IEEE Journal on Selected Areas in Communications
On-chip area-efficient binary sequence storage
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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Binary machines are a generalization of Feedback Shift Registers (FSRs) in which both, feedback and feedforward, connections are allowed and no chain connection between the register stages is required. In this paper, we present an algorithm for synthesis of binary machines with the minimum number of stages for a given degree of parallelization. Our experimental results show that for sequences with high linear complexity such as complementary, Legendre, or truly random, parallel binary machines are an order of magnitude smaller than parallel FSRs generating the same sequence. The presented approach can potentially be of advantage for many applications including wireless communication, cryptography, and testing.