On-chip area-efficient binary sequence storage

Authors:
Nan Li;Elena Dubrova
Affiliations:
Royal Institute of Technology, Stockholm, Sweden;Royal Institute of Technology, Stockholm, Sweden
Venue:
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Year:
2013

Citing 3
Cited 0

Pattern generation for a deterministic BIST scheme

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Synthesis of parallel binary machines

Proceedings of the International Conference on Computer-Aided Design
Optimal binary sequences for spread spectrum multiplexing (Corresp.)

IEEE Transactions on Information Theory

Quantified Score

Hi-index	0.00

Visualization

Abstract

On-chip storage of binary sequences normally require the use of Read-Only Memories (ROMs). However, ROMs do not exploit of the fact that the stored information is accessed sequentially. This paper presents an area-efficient sequence storage technique based on state machines. Experimental results show that the presented method significantly outperforms previous approaches. The resulting state machines are on average 54% smaller than ROMs storing the same sequence.