A Compact Rijndael Hardware Architecture with S-Box Optimization
ASIACRYPT '01 Proceedings of the 7th International Conference on the Theory and Application of Cryptology and Information Security: Advances in Cryptology
Lightweight privacy preserving authentication for RFID using a stream cipher
FSE'10 Proceedings of the 17th international conference on Fast software encryption
692-nW advanced encryption standard (AES) on a 0.13-µm CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The PHOTON family of lightweight Hash functions
CRYPTO'11 Proceedings of the 31st annual conference on Advances in cryptology
Synthesis of parallel binary machines
Proceedings of the International Conference on Computer-Aided Design
An improved hardware implementation of the grain-128a stream cipher
ICISC'12 Proceedings of the 15th international conference on Information Security and Cryptology
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This chapter presents detailed hardware implementation results and performance metrics for the eSTREAM candidate stream ciphers remaining in the Phase 3 hardware profile. Performance assessment has been made in accordance with the eSTREAM hardware testing framework in terms of power, area and speed. An attempt has been made to quantify the flexibility and scalability dimensions of performance. The results are presented in tabular and graphical format together with summarising the utility of the candidates against two notional applications: one for 10Mbps wireless network and a second for 100kHz RFID. Where applicable to a particular cipher, guidance on any limitations on the choice of key or IV is given. The chapter concludes with a summary of the performance of each of the candidates and some general guidance for future low resource hardware stream cipher development.