692-nW advanced encryption standard (AES) on a 0.13-µm CMOS

Authors:
Tim Good;Mohammed Benaissa
Affiliations:
Department of Electrical and Electronic Engineering, University of Sheffield, Sheffield, UK;Department of Electrical and Electronic Engineering, University of Sheffield, Sheffield, UK
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2010

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Abstract

This paper presents a very low power/area design for the advanced encryption standard (AES) based on an 8-bit data path. The average measured core power on a 0.13-µm CMOS using a 100-kHz clock and a core voltage of 0.75 V is 692 nW. The core area is 21 000 µm2 and the latency is 356 cycles. This design further challenges the low-resource end of the design space and is the first reported submicrowatt design for the AES; it has significant power-latency-area performance improvements over the previous state-of-the-art application-specific IC (ASIC) implementations.