Introduction to finite fields and their applications
Introduction to finite fields and their applications
A fully pipelined memoryless 17.8 Gbps AES-128 encryptor
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
An ASIC Implementation of the AES SBoxes
CT-RSA '02 Proceedings of the The Cryptographer's Track at the RSA Conference on Topics in Cryptology
A Compact Rijndael Hardware Architecture with S-Box Optimization
ASIACRYPT '01 Proceedings of the 7th International Conference on the Theory and Application of Cryptology and Information Security: Advances in Cryptology
Efficient Rijndael Encryption Implementation with Composite Field Arithmetic
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
An Optimized S-Box Circuit Architecture for Low Power AES Design
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
A 10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box Architecture
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
A systematic evaluation of compact hardware implementations for the rijndael s-box
CT-RSA'05 Proceedings of the 2005 international conference on Topics in Cryptology
Area, delay, and power characteristics of standard-cell implementations of the AES S-Box
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
On the Power of Bitslice Implementation on Intel Core2 Processor
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
A Lightweight Concurrent Fault Detection Scheme for the AES S-Boxes Using Normal Basis
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
Light-Weight Instruction Set Extensions for Bit-Sliced Cryptography
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
A Practical DPA Countermeasure with BDD Architecture
CARDIS '08 Proceedings of the 8th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Applications
Using Normal Bases for Compact Hardware Implementations of the AES S-Box
SCN '08 Proceedings of the 6th international conference on Security and Cryptography for Networks
Dual-rail transition logic: A logic style for counteracting power analysis attacks
Computers and Electrical Engineering
An Unequal Secure Encryption Scheme for H.264/AVC Video Compression Standard
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Secure Hardware Implementation of Non-linear Functions in the Presence of Glitches
Information Security and Cryptology --- ICISC 2008
Vulnerability modeling of cryptographic hardware to power analysis attacks
Integration, the VLSI Journal
Faster and Timing-Attack Resistant AES-GCM
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Journal of Electronic Testing: Theory and Applications
A compact ASIC implementation of the advanced encryption standard with concurrent error detection
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
A Comparative Study of Mutual Information Analysis under a Gaussian Assumption
Information Security Applications
Efficient implementations of some tweakable enciphering schemes in reconfigurable hardware
INDOCRYPT'07 Proceedings of the cryptology 8th international conference on Progress in cryptology
Implementation of the AES-128 on virtex-5 FPGAs
AFRICACRYPT'08 Proceedings of the Cryptology in Africa 1st international conference on Progress in cryptology
A very compact "Perfectly masked" S-box for AES
ACNS'08 Proceedings of the 6th international conference on Applied cryptography and network security
Boosting AES performance on a tiny processor core
CT-RSA'08 Proceedings of the 2008 The Cryptopgraphers' Track at the RSA conference on Topics in cryptology
Implementation and benchmarking of hardware accelerators for ciphering in LTE terminals
GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
International Journal of High Performance Systems Architecture
Proceedings of the ACM SIGCOMM 2010 conference
A low overhead DPA countermeasure circuit based on ring oscillators
IEEE Transactions on Circuits and Systems II: Express Briefs
Correlation-enhanced power analysis collision attack
CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
Mixed bases for efficient inversion in F((22)2)2 and conversion matrices of SubBytes of AES
CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
Provably secure higher-order masking of AES
CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
Algebraic side-channel analysis in the presence of errors
CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
692-nW advanced encryption standard (AES) on a 0.13-µm CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cryptanalysis of CLEFIA using differential methods with cache trace patterns
CT-RSA'11 Proceedings of the 11th international conference on Topics in cryptology: CT-RSA 2011
Pushing the limits: a very compact and a threshold implementation of AES
EUROCRYPT'11 Proceedings of the 30th Annual international conference on Theory and applications of cryptographic techniques: advances in cryptology
The PHOTON family of lightweight Hash functions
CRYPTO'11 Proceedings of the 31st annual conference on Advances in cryptology
Instruction set extensions for efficient AES implementation on 32-bit processors
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Intra-masking dual-rail memory on LUT implementation for tamper-resistant AES on FPGA
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Embedded SFE: offloading server and network using hardware tokens
FC'10 Proceedings of the 14th international conference on Financial Cryptography and Data Security
Area, delay, and power characteristics of standard-cell implementations of the AES s-box
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Low power AES hardware architecture for radio frequency identification
IWSEC'06 Proceedings of the 1st international conference on Security
SPN-hash: improving the provable resistance against differential collision attacks
AFRICACRYPT'12 Proceedings of the 5th international conference on Cryptology in Africa
Towards super-exponential side-channel security with efficient leakage-resilient PRFs
CHES'12 Proceedings of the 14th international conference on Cryptographic Hardware and Embedded Systems
CT-RSA'13 Proceedings of the 13th international conference on Topics in Cryptology
Putting together what fits together: grÆstl
CARDIS'12 Proceedings of the 11th international conference on Smart Card Research and Advanced Applications
CARDIS'12 Proceedings of the 11th international conference on Smart Card Research and Advanced Applications
Low-power compact composite field AES S-Box/Inv S-Box design in 65nm CMOS using Novel XOR Gate
Integration, the VLSI Journal
Efficient hardware implementation of the stream cipher WG-16 with composite field arithmetic
Proceedings of the 3rd international workshop on Trustworthy embedded devices
Secure and efficient design of software block cipher implementations on microcontrollers
International Journal of Grid and Utility Computing
Design space exploration of the lightweight stream cipher WG-8 for FPGAs and ASICs
Proceedings of the Workshop on Embedded Systems Security
Cancellation-Free circuits in unbounded and bounded depth
FCT'13 Proceedings of the 19th international conference on Fundamentals of Computation Theory
Stealthy dopant-level hardware trojans
CHES'13 Proceedings of the 15th international conference on Cryptographic Hardware and Embedded Systems
International Journal of Mobile Network Design and Innovation
AES side-channel countermeasure using random tower field constructions
Designs, Codes and Cryptography
Fully homomorphic SIMD operations
Designs, Codes and Cryptography
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A key step in the Advanced Encryption Standard (AES) algorithm is the “S-box.” Many implementations of AES have been proposed, for various goals, that effect the S-box in various ways. In particular, the most compact implementations to date of Satoh et al.[14] and Mentens et al.[6] perform the 8-bit Galois field inversion of the S-box using subfields of 4 bits and of 2 bits. Our work refines this approach to achieve a more compact S-box. We examined many choices of basis for each subfield, not only polynomial bases as in previous work, but also normal bases, giving 432 cases. The isomorphism bit matrices are fully optimized, improving on the “greedy algorithm.” Introducing some NOR gates gives further savings. The best case improves on [14] by 20%. This decreased size could help for area-limited hardware implementations, e.g., smart cards, and to allow more copies of the S-box for parallelism and/or pipelining of AES.