FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
AES Algorithm Implementation-An efficient approach for Sequential and Pipeline Architectures
ENC '03 Proceedings of the 4th Mexican International Conference on Computer Science
ITCC '04 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2 - Volume 2
A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
AES on FPGA from the fastest to the smallest
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
DSPs, BRAMs, and a Pinch of Logic: Extended Recipes for AES on FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Resource efficient implementation of T-Boxes in AES on Virtex-5 FPGA
Information Processing Letters
High performance GHASH function for long messages
ACNS'10 Proceedings of the 8th international conference on Applied cryptography and network security
Hardware framework for the rabbit stream cipher
Inscrypt'09 Proceedings of the 5th international conference on Information security and cryptology
Putting together what fits together: grÆstl
CARDIS'12 Proceedings of the 11th international conference on Smart Card Research and Advanced Applications
Authenticated storage using small trusted hardware
Proceedings of the 2013 ACM workshop on Cloud computing security workshop
Analyzing and comparing the AES architectures for their power consumption
Journal of Intelligent Manufacturing
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This paper presents an updated implementation of the Advanced Encryption Standard (AES) on the recent Xilinx Virtex-5 FPGAs. We show how a modified slice structure in these reconfigurable hardware devices results in significant improvement of the design efficiency. In particular, a single substitution box of the AES can fit in 8 FPGA slices. We combine these technological changes with a sound intertwining of the round and key round functionalities in order to produce encryption and decryption architectures that perfectly fit with the Digital Cinema Initiative specifications. More generally, our implementations are convenient for any application requiring Gbps-range throughput.