Selecting Cryptographic Key Sizes
PKC '00 Proceedings of the Third International Workshop on Practice and Theory in Public Key Cryptography: Public Key Cryptography
Efficient Rijndael Encryption Implementation with Composite Field Arithmetic
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
CARDIS '98 Proceedings of the The International Conference on Smart Card Research and Applications
Architectural Design Features of a Programmable High Throughput AES Coprocessor
ITCC '04 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2 - Volume 2
Power-efficient ASIC synthesis of cryptographic sboxes
Proceedings of the 14th ACM Great Lakes symposium on VLSI
A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors
IEEE Transactions on Computers
A Survey of Lightweight-Cryptography Implementations
IEEE Design & Test
IEEE Transactions on Computers
Implementation of the AES-128 on virtex-5 FPGAs
AFRICACRYPT'08 Proceedings of the Cryptology in Africa 1st international conference on Progress in cryptology
Journal of Intelligent Manufacturing
AES on FPGA from the fastest to the smallest
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Dynamic explicitly specified behaviors in distributed agent-based industrial solutions
Journal of Intelligent Manufacturing
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It has been a decade since the block cipher Rijndael--with some minor changes--takes the name AES (Advanced Encryption Standard) and becomes the new block cipher standard of US government. Over the passed years, through deeper analysis and conducted measurements, AES has gained significant confidence for its security. Meanwhile, the sophistication in its realizations has also evolved considerably; system designers are now able to choose a suitable AES architecture tailored for their area and performance needs. Couple of years ago, the wider technological trend has shifted towards the power aware system design, hence, low power AES architectures gain importance over area and performance oriented designs. In this study, we examine and employ the low power design techniques in reducing the power consumption. These efforts allow us to come up with a slightly different architecture for s-box module. As a result, the power consumptions of AES over the Field Programmable Gate Arrays (FPGAs) are reduced. All described work and respective measurements are carried on Xilinx FPGA families and possible comparisons are made with the existing literature.