Architectural Design Features of a Programmable High Throughput AES Coprocessor

Authors:
Alireza Hodjat;Patrick Schaumont;Ingrid Verbauwhede
Affiliations:
-;-;-
Venue:
ITCC '04 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2 - Volume 2
Year:
2004

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Abstract

Programmable, high throughput domain specific cryptoprocessors are required for different networkingapplications. This paper presents the architectural designfeatures that lead to a multiple Gbits/s rate AEScoprocessor, which is programmable with domainspecific instructions for Gbit throughput IPSec and otherapplications. Our design is a loosely coupled,independently working crypto-coprocessor that runs AESin ECB, CBC-MAC, Counter, and CCM modes ofoperation at a maximum throughput of 3.43 Gbits/s in a0.18-驴m CMOS technology without any penalty inthroughput for any of the above modes.