CT-RSA 2001 Proceedings of the 2001 Conference on Topics in Cryptology: The Cryptographer's Track at RSA
An ASIC Implementation of the AES SBoxes
CT-RSA '02 Proceedings of the The Cryptographer's Track at the RSA Conference on Topics in Cryptology
Streaming Encryption for a Secure Wavelength and Time Domain Hopped Optical Network
ITCC '04 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2 - Volume 2
A 10-Gbps full-AES crypto design with a twisted BDD S-box architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An area optimized reconfigurable encryptor for AES-Rijndael
Proceedings of the conference on Design, automation and test in Europe
IEEE Transactions on Computers
High-performance public-key cryptoprocessor for wireless mobile applications
Mobile Networks and Applications
Fast composite field S-box architectures for advanced encryption standard
Proceedings of the 18th ACM Great Lakes symposium on VLSI
A Lightweight Concurrent Fault Detection Scheme for the AES S-Boxes Using Normal Basis
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
Chai-Tea, Cryptographic Hardware Implementations of xTEA
INDOCRYPT '08 Proceedings of the 9th International Conference on Cryptology in India: Progress in Cryptology
Journal of Electronic Testing: Theory and Applications
Design and Hardware Implementation of QoSS-AES Processor for Multimedia applications
Transactions on Data Privacy
A high-speed AES architecture implementation
Proceedings of the 7th ACM international conference on Computing frontiers
A direction to avoid re-encryption in cryptographic file sharing
NPC'07 Proceedings of the 2007 IFIP international conference on Network and parallel computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical fault injection: quantified error and confidence
Proceedings of the Conference on Design, Automation and Test in Europe
Secure arithmetic coding with error detection capability
EURASIP Journal on Information Security
Design and implementation of a multi-core crypto-processor for software defined radios
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
FastCrypto: parallel AES pipelines extension for general-purpose processors
Neural, Parallel & Scientific Computations
FPGA implementation and performance evaluation of a high throughput crypto coprocessor
Journal of Parallel and Distributed Computing
Design of an ultra high speed AES processor for next generation IT security
Computers and Electrical Engineering
Automated design of cryptographic devices resistant to multiple side-channel attacks
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Cryptanalysis of the Full AES Using GPU-Like Special-Purpose Hardware
Fundamenta Informaticae - Cryptology in Progress: 10th Central European Conference on Cryptology, Będlewo Poland, 2010
Low-latency encryption: is "Lightweight = light + wait"?
CHES'12 Proceedings of the 14th international conference on Cryptographic Hardware and Embedded Systems
Analyzing and comparing the AES architectures for their power consumption
Journal of Intelligent Manufacturing
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This paper explores the area-throughput trade-off for an ASIC implementation of the Advanced Encryption Standard (AES). Different pipelined implementations of the AES algorithm as well as the design decisions and the area optimizations that lead to a low area and high throughput AES encryption processor are presented. With loop unrolling and outer-round pipelining techniques, throughputs of 30 Gbits/s to 70 Gbits/s are achievable in a 0.18-µm CMOS technology. Moreover, by pipelining the composite field implementation of the byte substitution phase of the AES algorithm (inner-round pipelining), the area consumption is reduced up to 35 percent. By designing an offline key scheduling unit for the AES processor the area cost is further reduced by 28 percent, which results in a total reduction of 48 percent while the same throughput is maintained. Therefore, the over 30 Gbits/s, fully pipelined AES processor operating in the counter mode of operation can be used for the encryption of data on optical links.