Use of elliptic curves in cryptography
Lecture notes in computer sciences; 218 on Advances in cryptology---CRYPTO 85
Algebraic aspects of cryptography
Algebraic aspects of cryptography
Elliptic curves in cryptography
Elliptic curves in cryptography
A method for obtaining digital signatures and public-key cryptosystems
Communications of the ACM
CM-Curves with Good Cryptographic Properties
CRYPTO '91 Proceedings of the 11th Annual International Cryptology Conference on Advances in Cryptology
A Fast Parallel Elliptic Curve Multiplication Resistant against Side Channel Attacks
PKC '02 Proceedings of the 5th International Workshop on Practice and Theory in Public Key Cryptosystems: Public Key Cryptography
Fast Multiplication on Elliptic Curves over GF(2m) without Precomputation
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
The Montgomery Powering Ladder
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
A Scalable Dual-Field Elliptic Curve Cryptographic Processor
IEEE Transactions on Computers
Guide to Elliptic Curve Cryptography
Guide to Elliptic Curve Cryptography
Interactive Cosimulation with Partial Evaluation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
High Performance FPGA based Elliptic Curve Cryptographic Co-Processor
ITCC '04 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2 - Volume 2
A Parallelized Design for an Elliptic Curve Cryptosystem Coprocessor
ITCC '05 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'05) - Volume I - Volume 01
Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors
IEEE Transactions on Computers
HW/SW co-design of a hyperelliptic curve cryptosystem using a microcode instruction set coprocessor
Integration, the VLSI Journal - Special issue: Embedded cryptographic hardware
Customizable elliptic curve cryptosystems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Superscalar coprocessor for high-speed curve-based cryptography
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
A highly efficient cipher processor for dual-field elliptic curve cryptography
IEEE Transactions on Circuits and Systems II: Express Briefs
pSHS: a scalable parallel software implementation of Montgomery multiplication for multicore systems
Proceedings of the Conference on Design, Automation and Test in Europe
Scan-based attack against elliptic curve cryptosystems
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
A high-performance unified-field reconfigurable cryptographic processor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Prime field ECDSA signature processing for reconfigurable embedded systems
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and evaluation of parallel, scalable, curve based processor over binary field
WSEAS Transactions on Computers
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
CHES'12 Proceedings of the 14th international conference on Cryptographic Hardware and Embedded Systems
Low-energy encryption for medical devices: security adds an extra design dimension
Proceedings of the 50th Annual Design Automation Conference
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This paper presents a reconfigurable curve-based cryptoprocessor that accelerates scalar multiplication of Elliptic Curve Cryptography (ECC) and HyperElliptic Curve Cryptography (HECC) of genus 2 over GF(2n). By allocating α copies of processing cores that embed reconfigurable Modular Arithmetic Logic Units (MALUs) over GF(2^n), the scalar multiplication of ECC/HECC can be accelerated by exploiting Instruction-Level Parallelism (ILP). The supported field size can be arbitrary up to α(n + 1) - 1. The superscaling feature is facilitated by defining a single instruction that can be used for all field operations and point/divisor operations. In addition, the cryptoprocessor is fully programmable and it can handle various curve parameters and arbitrary irreducible polynomials. The cost, performance, and security trade-offs are thoroughly discussed for different hardware configurations and software programs. The synthesis results with a 0:13-μm CMOS technology show that the proposed reconfigurable cryptoprocessor runs at 292 MHz, whereas the field sizes can be supported up to 587 bits. The compact and fastest configuration of our design is also synthesized with a fixed field size and irreducible polynomial. The results show that the scalar multiplication of ECC over GF(2163) and HECC over GF(283) can be performed in 29 and 63 μs, respectively.