VLSI Architectures for Computing Multiplications and Inverses in GF(2m)
IEEE Transactions on Computers
Introduction to finite fields and their applications
Introduction to finite fields and their applications
A fast algorithm for computing multiplicative inverses in GF(2m) using normal bases
Information and Computation
Optimal normal bases in GF(pn)
Discrete Applied Mathematics
A fast elliptic curve cryptosystem
EUROCRYPT '89 Proceedings of the workshop on the theory and application of cryptographic techniques on Advances in cryptology
Implementing elliptic curve cryptography
Implementing elliptic curve cryptography
The State of Elliptic Curve Cryptography
Designs, Codes and Cryptography - Special issue on towards a quarter-century of public key cryptography
Elliptic curves in cryptography
Elliptic curves in cryptography
An Efficient Optimal Normal Basis Type II Multiplier
IEEE Transactions on Computers
Elliptic curve cryptography on smart cards without coprocessors
Proceedings of the fourth working conference on smart card research and advanced applications on Smart card research and advanced applications
Generic implementations of elliptic curve cryptography using partial reduction
Proceedings of the 9th ACM conference on Computer and communications security
Reconfigurable Implementation of Elliptic Curve Crypto Algorithms
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Software Implementation of the NIST Elliptic Curves Over Prime Fields
CT-RSA 2001 Proceedings of the 2001 Conference on Topics in Cryptology: The Cryptographer's Track at RSA
Efficient Software Implementation for Finite Field Multiplication in Normal Basis
ICICS '01 Proceedings of the Third International Conference on Information and Communications Security
Fully Parameterizable Elliptic Curve Cryptography Processor over GF(2)
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Fast Multiplication on Elliptic Curves over GF(2m) without Precomputation
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Elliptic Curve Scalar Multiplier Design Using FPGAs
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
A High Performance Reconfigurable Elliptic Curve Processor for GF(2m)
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
An Energy Efficient Reconfigurable Public-Key Cryptograhpy Processor Architecture
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
Software Implementation of Elliptic Curve Cryptography over Binary Fields
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
A Scalable GF(p) Elliptic Curve Processor Architecture for Programmable Hardware
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
The Hessian Form of an Elliptic Curve
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
A Reconfigurable System on Chip Implementation for Elliptic Curve Cryptography over GF(2n)
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
An End-to-End Systems Approach to Elliptic Curve Cryptography
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Implementation of Elliptic Curve Cryptographic Coprocessor over GF(2m) on an FPGA
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
A Scalable Dual-Field Elliptic Curve Cryptographic Processor
IEEE Transactions on Computers
Hardware architectures for public key cryptography
Integration, the VLSI Journal
Rapid Prototyping for Hardware Accelerated Elliptic Curve Public-Key Cryptosystems
RSP '01 Proceedings of the 12th International Workshop on Rapid System Prototyping
Guide to Elliptic Curve Cryptography
Guide to Elliptic Curve Cryptography
Parallel Multipliers Based on Special Irreducible Pentanomials
IEEE Transactions on Computers
High Performance FPGA based Elliptic Curve Cryptographic Co-Processor
ITCC '04 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2 - Volume 2
An FPGA implementation of an elliptic curve processor GF(2m)
Proceedings of the 14th ACM Great Lakes symposium on VLSI
A microcoded elliptic curve processor using FPGA technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computers
Fast elliptic curve cryptography on FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast point multiplication on Koblitz curves: Parallelization method and implementations
Microprocessors & Microsystems
On parallelization of high-speed processors for elliptic curve cryptography
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Knapsack based ECC for digital signature authentication
International Journal of Communication Networks and Distributed Systems
Flexible hardware processor for elliptic curve cryptography over NIST prime fields
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Robust Software Partitioning with Multiple Instantiation
INFORMS Journal on Computing
Cryptography with fast point multiplication by using ASCII codes and its implementation
International Journal of Communication Networks and Distributed Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new elliptic curve cryptosystem for securing sensitive data applications
International Journal of Electronic Security and Digital Forensics
| Hi-index | 0.00 |
This paper presents a method for producing hardware designs for elliptic curve cryptography (ECC) systems over the finite field GF(2m), using the optimal normal basis for the representation of numbers. Our field multiplier design is based on a parallel architecture containing multiple -bit serial multipliers; by changing the number of such serial multipliers, designers can obtain implementations with different tradeoffs in speed, size and level of security. A design generator has been developed which can automatically produce a customised ECC hardware design that meets user-defined requirements. To facilitate performance characterization, we have developed a parametric model for estimating the number of cycles for our generic ECC architecture. The resulting hardware implementations are among the fastest reported: for a key size of 270 bits, a point multiplication in a Xilinx XC2V6000 FPGA at 35 MHz can run over 1000 times faster than a software implementation on a Xeon computer at 2.6 GHz.