VLSI Architectures for Computing Multiplications and Inverses in GF(2m)
IEEE Transactions on Computers
Discrete Applied Mathematics
A survey of fast exponentiation methods
Journal of Algorithms
CM-Curves with Good Cryptographic Properties
CRYPTO '91 Proceedings of the 11th Annual International Cryptology Conference on Advances in Cryptology
Reconfigurable Implementation of Elliptic Curve Crypto Algorithms
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Exploration of Design Space in ECDSA
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A High Performance Reconfigurable Elliptic Curve Processor for GF(2m)
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
A Scalable GF(p) Elliptic Curve Processor Architecture for Programmable Hardware
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
A Scalable Dual-Field Elliptic Curve Cryptographic Processor
IEEE Transactions on Computers
Hardware architectures for public key cryptography
Integration, the VLSI Journal
An FPGA implementation of an elliptic curve processor GF(2m)
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Elliptic and hyperelliptic curves on embedded μP
ACM Transactions on Embedded Computing Systems (TECS)
On-demand design service innovations
IBM Journal of Research and Development
A unified architecture for a public key cryptographic coprocessor
Journal of Systems Architecture: the EUROMICRO Journal
Customizable elliptic curve cryptosystems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A compact fast elliptic curve scalar multiplier with variable key size is implemented as a coprocessor with a Xilinx FPGA. This implementation utilizes the internal SRAM/registers of the FPGA and has the whole scalar multiplier implemented within a single FPGA chip. The compact design helps reduce the overhead and limitations associated with data transfer between FPGA and host, and thus leads to high performance. The experimental data from the mappings over small fields shows that the carefully constructed hardware architecture is regular and has high CLB utilization.