Fault-tolerant decoders for cyclic error-correcting codes
IEEE Transactions on Computers
VLSI implementation of public-key encryption algorithms
Proceedings on Advances in cryptology---CRYPTO '86
A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases
IEEE Transactions on Computers
A New Bit-Serial Systolic Multiplier Over GF(2/sup m/)
IEEE Transactions on Computers
A New Algorithm for Multiplication in Finite Fields
IEEE Transactions on Computers
A VLSI Architecture for Fast Inversion in GF(2/sup m/)
IEEE Transactions on Computers
An Algorithm to Design Finite Field Multipliers Using a Self-Dual Normal Basis
IEEE Transactions on Computers
AT/sup 2/-Optimal Galois Field Multiplier for VLSI
IEEE Transactions on Computers
IEEE Transactions on Computers
Constructing normal bases in finite fields
Journal of Symbolic Computation
IEEE Transactions on Computers - Special issue on computer arithmetic
Bit-Serial Systolic Divider and Multiplier for Finite Fields GF(2/sup m/)
IEEE Transactions on Computers - Special issue on computer arithmetic
A Design of Reed-Solomon Decoder with Systolic-Array Structure
IEEE Transactions on Computers
A combinatorial treatment of balancing networks
Journal of the ACM (JACM)
Efficient Multiplier Architectures for Galois Fields GF(24n)
IEEE Transactions on Computers
Low-Complexity Bit-Parallel Canonical and Normal Basis Multipliers for a Class of Finite Fields
IEEE Transactions on Computers
Low Complexity Bit-Parallel Multipliers for a Class of Finite Fields
IEEE Transactions on Computers
Systolic Array Implementation of Euclid's Algorithm for Inversion and Division in GF (2m)
IEEE Transactions on Computers
Low-Energy Digit-Serial/Parallel Finite Field Multipliers
Journal of VLSI Signal Processing Systems - Special issue on application specific systems, architectures and processors
IEEE Transactions on Computers
Double-Basis Multiplicative Inversion Over GF(2m)
IEEE Transactions on Computers
New Systolic Arrays for C + AB2, Inversion, and Division in GF(2m)
IEEE Transactions on Computers
A Fast Algorithm for Multiplicative Inversion in GF(2m) Using Normal Basis
IEEE Transactions on Computers
A new hardware architecture for operations In GF (2m)
IEEE Transactions on Computers
A New Construction of Massey-Omura Parallel Multiplier over GF(2^{m})
IEEE Transactions on Computers
Montgomery Multiplier and Squarer for a Class of Finite Fields
IEEE Transactions on Computers
A New Hardware Architecture for Operations in GF(2m)
IEEE Transactions on Computers
Architectures for Exponentiation Over GD(2/sup n/) Adopted for Smartcard Application
IEEE Transactions on Computers
On Computing Multiplicative Inverses in GF(2/sup m/)
IEEE Transactions on Computers
A Systolic Architecture for Computing Inverses and Divisions in Finite Fields GF(2/sup m/)
IEEE Transactions on Computers
A Modified Massey-Omura Parallel Multiplier for a Class of Finite Fields
IEEE Transactions on Computers
A Systolic Power-Sum Circuit for GF(2/sup m/)
IEEE Transactions on Computers
GF(2m) Multiplication and Division Over the Dual Basis
IEEE Transactions on Computers
IEEE Transactions on Computers
A Search of Minimal Key Functions for Normal Basis Multipliers
IEEE Transactions on Computers
Finite Field Multiplier Using Redundant Representation
IEEE Transactions on Computers
Architectures and VLSI Implementations of the AES-Proposal Rijndael
IEEE Transactions on Computers
Reconfigurable Implementation of Elliptic Curve Crypto Algorithms
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
On Efficient Normal Basis Multiplication
INDOCRYPT '00 Proceedings of the First International Conference on Progress in Cryptology
A New Aspect of Dual Basis for Efficient Field Arithmetic
PKC '99 Proceedings of the Second International Workshop on Practice and Theory in Public Key Cryptography
Highly Regular Architectures for Finite Field Computation Using Redundant Basis
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Elliptic Curve Scalar Multiplier Design Using FPGAs
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Efficient Multiplication Beyond Optimal Normal Bases
IEEE Transactions on Computers
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A Compact Fast Variable Key Size Elliptic Curve Cryptosystem Coprocessor
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Architectures for Arithmetic over GF(2^m)
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Hardware architectures for public key cryptography
Integration, the VLSI Journal
Systolic architectures for inversion/division using AB2 circuits in GF(2m)
Integration, the VLSI Journal
High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m)
IEEE Transactions on Computers
Efficient scalable VLSI architecture for Montgomery inversion in GF(p)
Integration, the VLSI Journal
Efficient digit-serial normal basis multipliers over binary extension fields
ACM Transactions on Embedded Computing Systems (TECS)
Low Complexity Word-Level Sequential Normal Basis Multipliers
IEEE Transactions on Computers
Hardware and Software Normal Basis Arithmetic for Pairing-Based Cryptography in Characteristic Three
IEEE Transactions on Computers
Efficient Algorithms and Architectures for Field Multiplication Using Gaussian Normal Bases
IEEE Transactions on Computers
A New Approach to Subquadratic Space Complexity Parallel Multipliers for Extended Binary Fields
IEEE Transactions on Computers
Reconfigurable system for high-speed and diversified AES using FPGA
Microprocessors & Microsystems
Comb Architectures for Finite Field Multiplication in F(2^m)
IEEE Transactions on Computers
Low-complexity versatile finite field multiplier in normal basis
EURASIP Journal on Applied Signal Processing
WG: A family of stream ciphers with designed randomness properties
Information Sciences: an International Journal
A multiplier to enhance the speed of encryption/decryption
ISP'06 Proceedings of the 5th WSEAS International Conference on Information Security and Privacy
A New Parallel Multiplier for Type II Optimal Normal Basis
Computational Intelligence and Security
FPGA Design of Self-certified Signature Verification on Koblitz Curves
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
A New Bit-Serial Architecture for Field Multiplication Using Polynomial Bases
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
Implementation and analysis of stream ciphers based on the elliptic curves
Computers and Electrical Engineering
Fast point multiplication on Koblitz curves: Parallelization method and implementations
Microprocessors & Microsystems
On parallelization of high-speed processors for elliptic curve cryptography
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-complexity bit-parallel multiplier over GF(2m) using dual basis representation
Journal of Computer Science and Technology
Algebraic decoding of the (41, 21, 9) Quadratic Residue code
Information Sciences: an International Journal
Low-complexity bit-parallel dual basis multipliers using the modified Booth's algorithm
Computers and Electrical Engineering
Concurrent error detection architectures for Gaussian normal basis multiplication over GF(2m)
Integration, the VLSI Journal
An extension of TYT inversion algorithm in polynomial basis
Information Processing Letters
Novel algebraic structure for cyclic codes
AAECC'07 Proceedings of the 17th international conference on Applied algebra, algebraic algorithms and error-correcting codes
High speed decoding of the binary (47,24,11) quadratic residue code
Information Sciences: an International Journal
On the decoding of the (24,12,8) Golay code
Information Sciences: an International Journal
A modified low complexity digit-level Gaussian normal basis multiplier
WAIFI'10 Proceedings of the Third international conference on Arithmetic of finite fields
Customizable elliptic curve cryptosystems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA implementation of point multiplication on koblitz curves using kleinian integers
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Fast forth power and its application in inversion computation for a special class of trinomials
ICCSA'10 Proceedings of the 2010 international conference on Computational Science and Its Applications - Volume Part II
A HIPAA-compliant key management scheme with revocation of authorization
Computer Methods and Programs in Biomedicine
| Hi-index | 15.09 |
Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that can be easily realized on VLSI chips. Massey and Omura [1] recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. In this paper, a pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable, and therefore, naturally suitable for VLSI implementation.