VLSI Architectures for Computing Multiplications and Inverses in GF(2m)
IEEE Transactions on Computers
Introduction to finite fields and their applications
Introduction to finite fields and their applications
Structure of parallel multipliers for a class of fields GF(2m)
Information and Computation
Discrete Applied Mathematics
IEEE Transactions on Computers - Special issue on computer arithmetic
Efficient Exponentiation of a Primitive Root in GF(2m)
IEEE Transactions on Computers
Low-Complexity Bit-Parallel Canonical and Normal Basis Multipliers for a Class of Finite Fields
IEEE Transactions on Computers
Low Complexity Bit-Parallel Multipliers for a Class of Finite Fields
IEEE Transactions on Computers
On-Line Error Detection for Bit-Serial Multipliers in GF(2m)
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Computers
New Low-Complexity Bit-Parallel Finite Field Multipliers Using Weakly Dual Bases
IEEE Transactions on Computers
Efficient Normal Basis Multipliers in Composite Fields
IEEE Transactions on Computers
An Efficient Optimal Normal Basis Type II Multiplier
IEEE Transactions on Computers
On the Inherent Space Complexity of Fast Parallel Multipliers for GF(2/supm/)
IEEE Transactions on Computers
A new hardware architecture for operations In GF (2m)
IEEE Transactions on Computers
A New Construction of Massey-Omura Parallel Multiplier over GF(2^{m})
IEEE Transactions on Computers
A New Hardware Architecture for Operations in GF(2m)
IEEE Transactions on Computers
Bit-Parallel Finite Field Multiplier and Squarer Using Polynomial Basis
IEEE Transactions on Computers
Finite Field Multiplier Using Redundant Representation
IEEE Transactions on Computers
Low Complexity Bit Serial Systolic Multipliers over GF(2m) for Three Classes of Finite Fields
ICICS '02 Proceedings of the 4th International Conference on Information and Communications Security
On Complexity of Polynomial Basis Squaring in F2m
SAC '00 Proceedings of the 7th Annual International Workshop on Selected Areas in Cryptography
Fast Normal Basis Multiplication Using General Purpose Processors
SAC '01 Revised Papers from the 8th Annual International Workshop on Selected Areas in Cryptography
On Efficient Normal Basis Multiplication
INDOCRYPT '00 Proceedings of the First International Conference on Progress in Cryptology
Efficient Bit Serial Multiplication Using Optimal Normal Bases of Type II in GF (2m)
ISC '02 Proceedings of the 5th International Conference on Information Security
Low Complexity Bit-Parallel Finite Field Arithmetic Using Polynomial Basis
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Highly Regular Architectures for Finite Field Computation Using Redundant Basis
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
A New Low Complexity Parallel Multiplier for a Class of Finite Fields
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Efficient Multiplication Beyond Optimal Normal Bases
IEEE Transactions on Computers
Architectures for Arithmetic over GF(2^m)
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Fast Normal Basis Multiplication Using General Purpose Processors
IEEE Transactions on Computers
Parallel Multipliers Based on Special Irreducible Pentanomials
IEEE Transactions on Computers
Efficient digit-serial normal basis multipliers over binary extension fields
ACM Transactions on Embedded Computing Systems (TECS)
Hardware and Software Normal Basis Arithmetic for Pairing-Based Cryptography in Characteristic Three
IEEE Transactions on Computers
IEEE Transactions on Computers
Bit-Parallel Finite Field Multipliers for Irreducible Trinomials
IEEE Transactions on Computers
Journal of VLSI Signal Processing Systems
Software Multiplication Using Gaussian Normal Bases
IEEE Transactions on Computers
A New Approach to Subquadratic Space Complexity Parallel Multipliers for Extended Binary Fields
IEEE Transactions on Computers
IEEE Transactions on Computers
Software Implementation of Arithmetic in
WAIFI '07 Proceedings of the 1st international workshop on Arithmetic of Finite Fields
Computers and Electrical Engineering
Unified parallel systolic multiplier over GF(2m)
Journal of Computer Science and Technology
Journal of Signal Processing Systems
A high-speed word level finite field multiplier in F2m using redundant representation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An extension of TYT inversion algorithm in polynomial basis
Information Processing Letters
Efficient architecture for exponentiation and division in GF(2m) using irreducible AOP
ICCSA'03 Proceedings of the 2003 international conference on Computational science and its applications: PartI
An efficient algorithm for computing inverses in GF(2m) using dual bases
ICCS'03 Proceedings of the 2003 international conference on Computational science
Modified serial multipliers for Type-IV gaussian normal bases
INDOCRYPT'05 Proceedings of the 6th international conference on Cryptology in India
Gauss periods as constructions of low complexity normal bases
Designs, Codes and Cryptography
VLSI performance evaluation and analysis of systolic and semisystolic finite field multipliers
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Unidirectional two dimensional systolic array for multiplication in GF(2m) using LSB first algorithm
WILF'05 Proceedings of the 6th international conference on Fuzzy Logic and Applications
Finite field arithmetic using quasi-normal bases
Finite Fields and Their Applications
Scalable Gaussian Normal Basis Multipliers over GF(2m) Using Hankel Matrix-Vector Representation
Journal of Signal Processing Systems
Information Processing Letters
| Hi-index | 15.05 |
A Massey-Omura parallel multiplier of finite fields GF(2/sup m/) contains m identical blocks whose inputs are cyclically shifted versions of one another. It is shown that for fields GF(2/sup m/) generated by irreducible all one polynomials, a portion of the block is independent of the input cyclic shift; hence, the multiplier contains redundancy. By removing the redundancy, a modified parallel multiplier is presented which is modular and has a lower circuit complexity.