A New Bit-Serial Systolic Multiplier Over GF(2/sup m/)
IEEE Transactions on Computers
Bit serial multiplication in finite fields
SIAM Journal on Discrete Mathematics
Efficient Multiplier Architectures for Galois Fields GF(24n)
IEEE Transactions on Computers
Mastrovito Multiplier for All Trinomials
IEEE Transactions on Computers
New Low-Complexity Bit-Parallel Finite Field Multipliers Using Weakly Dual Bases
IEEE Transactions on Computers
New Systolic Arrays for C + AB2, Inversion, and Division in GF(2m)
IEEE Transactions on Computers
IEEE Transactions on Computers
A Modified Massey-Omura Parallel Multiplier for a Class of Finite Fields
IEEE Transactions on Computers
Bit-Level Systolic Array for Fast Exponentiation in GF(2/sup m/)
IEEE Transactions on Computers
Low-Complexity Bit-Parallel Systolic Montgomery Multipliers for Special Classes of GF(2^m)
IEEE Transactions on Computers
Low-complexity bit-parallel systolic multipliers over GF(2m)
Integration, the VLSI Journal
Systolic Multipliers for Finite Fields GF(2m)
IEEE Transactions on Computers
Efficient semisystolic architectures for finite-field arithmetic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bit-serial Reed - Solomon encoders
IEEE Transactions on Information Theory
On bit-serial multiplication and dual bases in GF(2m)
IEEE Transactions on Information Theory
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Systolic arrays for multiplication in GF(2^m) of Yeh et al. with LSB (least significant bit) first algorithm have the unfavorable properties such as increased area complexity and bidirectional data flows compared with the arrays of Wang and Lin with MSB (most significant bit) first algorithm. In this paper, by using a polynomial basis with LSB first algorithm, we present new bit parallel and bit serial systolic arrays over GF(2^m). Our bit parallel systolic multiplier has unidirectional data flows with seven latches in each basic cell. Also our bit serial systolic array has only one control signal with eight latches in each basic cell. Thus our new arrays with LSB first algorithm have shorter critical path delay, comparable hardware complexity, and have the same unidirectional data flows compared with the arrays using MSB first algorithm. We also present new linear systolic arrays for multiplication in GF(2^m) using irreducible trinomial x^m+x^k+1. It is shown that our linear arrays with trinomial basis have reduced hardware complexity since they require two fewer latches than the linear systolic arrays using general irreducible polynomials.