A New Bit-Serial Systolic Multiplier Over GF(2/sup m/)

Authors:
B. B. Zhou
Affiliations:
Australian National University, Canberra, Australia
Venue:
IEEE Transactions on Computers
Year:
1988

Citing 2
Cited 6

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Introduction to VLSI Systems

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Bit-Serial Systolic Divider and Multiplier for Finite Fields GF(2/sup m/)

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Novel Radix Finite Field Multiplier for GF(2^m)

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Low-complexity bit-parallel systolic multipliers over GF(2m)

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More efficient systolic arrays for multiplication in GF(2m) using LSB first algorithm with irreducible polynomials and trinomials

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ICCSA'05 Proceedings of the 2005 international conference on Computational Science and its Applications - Volume Part I
Unidirectional two dimensional systolic array for multiplication in GF(2m) using LSB first algorithm

WILF'05 Proceedings of the 6th international conference on Fuzzy Logic and Applications

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Abstract

A bit-serial systolic array has been developed to computer multiplications over GF(2/sup m/). In contrast to a previously designed systolic multiplier, this algorithm allows the input elements to center a linear systolic array in the same order, and the system only requires one control signal.