A New Bit-Serial Systolic Multiplier Over GF(2/sup m/)
IEEE Transactions on Computers
Structure of parallel multipliers for a class of fields GF(2m)
Information and Computation
Bit serial multiplication in finite fields
SIAM Journal on Discrete Mathematics
Efficient Multiplier Architectures for Galois Fields GF(24n)
IEEE Transactions on Computers
New Systolic Arrays for C + AB2, Inversion, and Division in GF(2m)
IEEE Transactions on Computers
IEEE Transactions on Computers
A Modified Massey-Omura Parallel Multiplier for a Class of Finite Fields
IEEE Transactions on Computers
Bit-Level Systolic Array for Fast Exponentiation in GF(2/sup m/)
IEEE Transactions on Computers
Systolic Multipliers for Finite Fields GF(2m)
IEEE Transactions on Computers
Efficient semisystolic architectures for finite-field arithmetic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ICCSA'05 Proceedings of the 2005 international conference on Computational Science and its Applications - Volume Part I
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The two dimensional systolic array for multiplication in binary field GF(2m) with LSB (Least Significant Bit) first algorithm proposed by Yeh et al. has the unfavorable property of bidirectional data flows compared with that of Wang and Lin which use MSB (Most Significant Bit) first algorithm. In this paper, by using a polynomial basis with LSB first algorithm, we present an improved bit parallel systolic array over GF(2m). Our two dimensional systolic array has unidirectional data flows with 7 latches in each basic cell. Therefore our systolic array has a shorter critical path delay and has the same unidirectional data flows to the multipliers with MSB first scheme.