Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
VLSI Architectures for Computing Multiplications and Inverses in GF(2m)
IEEE Transactions on Computers
VLSI array processors
A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases
IEEE Transactions on Computers
A VLSI Architecture for Fast Inversion in GF(2/sup m/)
IEEE Transactions on Computers
Bit-Serial Systolic Divider and Multiplier for Finite Fields GF(2/sup m/)
IEEE Transactions on Computers - Special issue on computer arithmetic
Cryptography and data security
Cryptography and data security
A Systolic Architecture for Computing Inverses and Divisions in Finite Fields GF(2/sup m/)
IEEE Transactions on Computers
A Systolic Power-Sum Circuit for GF(2/sup m/)
IEEE Transactions on Computers
A Power-Sum Systolic Architecture in GF(2m)
ICOIN '02 Revised Papers from the International Conference on Information Networking, Wireless Communications Technologies and Network Applications-Part II
Efficient Power-Sum Systolic Architectures for Public-Key Cryptosystems in GF(2m)
COCOON '02 Proceedings of the 8th Annual International Conference on Computing and Combinatorics
Inversion/Division Systolic Architecture for Public-Key Cryptosystems in GF(2m)
ISC '02 Proceedings of the 5th International Conference on Information Security
Hardware architectures for public key cryptography
Integration, the VLSI Journal
Systolic architectures for inversion/division using AB2 circuits in GF(2m)
Integration, the VLSI Journal
New Systolic Architectures for Inversion and Division in GF(2^m)
IEEE Transactions on Computers
Low complexity bit-parallel systolic architecture for computing C + AB2 over a class of GF(2m)
Integration, the VLSI Journal
Area and time efficient AB2 multipliers based on cellular automata
Computer Standards & Interfaces
Elliptic curve based hardware architecture using cellular automata
Mathematics and Computers in Simulation
Computers and Electrical Engineering
IEEE Transactions on Circuits and Systems II: Express Briefs
Efficient architecture for exponentiation and division in GF(2m) using irreducible AOP
ICCSA'03 Proceedings of the 2003 international conference on Computational science and its applications: PartI
Cellular automata architecture for elliptic curve cryptographic hardware
ICCS'06 Proceedings of the 6th international conference on Computational Science - Volume Part III
Modular divider for elliptic curve cryptographic hardware based on programmable CA
ICCS'06 Proceedings of the 6th international conference on Computational Science - Volume Part IV
Evolutionary hardware architecture for division in elliptic curve cryptosystems over GF(2n)
ICNC'05 Proceedings of the First international conference on Advances in Natural Computation - Volume Part III
Unidirectional two dimensional systolic array for multiplication in GF(2m) using LSB first algorithm
WILF'05 Proceedings of the 6th international conference on Fuzzy Logic and Applications
| Hi-index | 14.98 |
In this paper, we present a new parallel-in parallel-out systolic array with unidirectional data flow for performing the power-sum operation C + AB2 in finite fields GF(2m). The architecture employs the standard basis representation and can provide the maximum throughput in the sense of producing new results at a rate of one per clock cycle. It is highly regular, modular, and, thus, well-suited to VLSI implementation. As compared to a previous systolic power-sum circuit with bidirectional data flow and the same throughput performance, the proposed one has smaller latency, consumes less chip area, and can more easily incorporate fault-tolerant design. Based on the new power-sum circuit, we also propose a parallel-in parallel-out systolic array with the maximum throughput for computing inverses/divisions in GF(2m). The proposed systolic divider gains advantages over an existing system with the same throughput performance in terms of chip area, latency, and fault tolerance.