VLSI array processors
A systolic array design methodology for sequential loop algorithms
A systolic array design methodology for sequential loop algorithms
Principles of digital design
Two systolic architectures for modular multiplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
New Systolic Arrays for C + AB2, Inversion, and Division in GF(2m)
IEEE Transactions on Computers
A Systolic Power-Sum Circuit for GF(2/sup m/)
IEEE Transactions on Computers
Low-Complexity Bit-Parallel Systolic Montgomery Multipliers for Special Classes of GF(2^m)
IEEE Transactions on Computers
Efficient semisystolic architectures for finite-field arithmetic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast VLSI arithmetic algorithms for high-security elliptic curve cryptographic applications
IEEE Transactions on Consumer Electronics
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Finite field arithmetic operations have been widely used in the areas of network security and data communication applications, and high-speed and low-complexity design for finite field arithmetic is very necessary for these applications. The current paper presents a new AB2 algorithm along with its systolic implementations in GF(2m). The proposed algorithm is based on the MSB-first scheme using the standard basis representation. In addition, parallel-in parallel-out systolic architectures are also introduced using this algorithm as a foundation. The proposed architectures have a low hardware complexity and small latency compared to conventional architectures. In particular, the hardware complexity of AB2 and inversion/division array are about 25% lower than Wang's over GF(2m), while the latency of AB2 and inversion/ division array are about 40% and 49.6% lower, respectively. Furthermore, since the proposed architectures incorporate simplicity, regularity, modularity, and pipelinability, they are well suited to VLSI implementation and can also be utilized as the basic architecture for a crypto-processor.