VLSI Architectures for Computing Multiplications and Inverses in GF(2m)
IEEE Transactions on Computers
IEEE Transactions on Computers
On the VLSI Design of a Pipeline Reed-Solomon Decoder Using Systolic Arrays
IEEE Transactions on Computers
Error Control Coding, Second Edition
Error Control Coding, Second Edition
Low-Energy Digit-Serial/Parallel Finite Field Multipliers
Journal of VLSI Signal Processing Systems - Special issue on application specific systems, architectures and processors
New Systolic Arrays for C + AB2, Inversion, and Division in GF(2m)
IEEE Transactions on Computers
IEEE Transactions on Computers
Low Complexity Bit Serial Systolic Multipliers over GF(2m) for Three Classes of Finite Fields
ICICS '02 Proceedings of the 4th International Conference on Information and Communications Security
A Power-Sum Systolic Architecture in GF(2m)
ICOIN '02 Revised Papers from the International Conference on Information Networking, Wireless Communications Technologies and Network Applications-Part II
Parallel Algorithm and Architecture for Public-Key Cryptosystem
EurAsia-ICT '02 Proceedings of the First EurAsian Conference on Information and Communication Technology
Efficient Power-Sum Systolic Architectures for Public-Key Cryptosystems in GF(2m)
COCOON '02 Proceedings of the 8th Annual International Conference on Computing and Combinatorics
Inversion/Division Systolic Architecture for Public-Key Cryptosystems in GF(2m)
ISC '02 Proceedings of the 5th International Conference on Information Security
Low complexity bit-parallel systolic architecture for computing C + AB2 over a class of GF(2m)
Integration, the VLSI Journal
Multiplexer-based bit-parallel systolic multipliers over GF(2m)
Computers and Electrical Engineering
Area and time efficient AB2 multipliers based on cellular automata
Computer Standards & Interfaces
Unified parallel systolic multiplier over GF(2m)
Journal of Computer Science and Technology
Low-complexity bit-parallel multiplier over GF(2m) using dual basis representation
Journal of Computer Science and Technology
Efficient architecture for exponentiation and division in GF(2m) using irreducible AOP
ICCSA'03 Proceedings of the 2003 international conference on Computational science and its applications: PartI
Computational algorithm and architecture for AB2 multiplication in finite fields
ICCSA'03 Proceedings of the 2003 international conference on Computational science and its applications: PartI
Efficient semisystolic architectures for finite-field arithmetic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A systolic power-sum circuit designed to perform AB/sup 2/+C computations in the finite field GF(2/sup m/) is presented, where A, B, and C are arbitrary elements of GF(2/sup m/). This new circuit is constructed by m/sup 2/ identical cells, each of which consists of three 2-input AND logical gates, one 2-input XOR gate, one 3-input XOR gate, and ten latches. The AB/sup 2/+C computation is required in decoding many error-correcting codes. The paper shows that a decoder implemented using the new power-sum circuit will have less complex circuitry and shorter decoding delay than one implemented using conventional product-sum multipliers.