VLSI Architectures for Computing Multiplications and Inverses in GF(2m)
IEEE Transactions on Computers
Finite field for scientists and engineers
Finite field for scientists and engineers
A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases
IEEE Transactions on Computers
Static Rate-Optimal Scheduling of Iterative Data-Flow Programs Via Optimum Unfolding
IEEE Transactions on Computers
Bit-Serial Systolic Divider and Multiplier for Finite Fields GF(2/sup m/)
IEEE Transactions on Computers - Special issue on computer arithmetic
HEAT: hierarchical energy analysis tool
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Digit-Serial Computation
Low Power Digital CMOS Design
VLSI Signal Processing; A Bit-Serial Approach
VLSI Signal Processing; A Bit-Serial Approach
Theory of Information and Coding
Theory of Information and Coding
A Systolic Power-Sum Circuit for GF(2/sup m/)
IEEE Transactions on Computers
GF(2m) Multiplication and Division Over the Dual Basis
IEEE Transactions on Computers
Efficient Finite Field Serial/Parallel Multiplication
ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Error Control Coding, Second Edition
Error Control Coding, Second Edition
Efficient semisystolic architectures for finite-field arithmetic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast Arithmetic for Public-Key Algorithms in Galois Fields with Composite Exponents
IEEE Transactions on Computers
Look-Up Table-Based Large Finite Field Multiplication in Memory Constrained Cryptosystems
IEEE Transactions on Computers - Special issue on computer arithmetic
Generic implementations of elliptic curve cryptography using partial reduction
Proceedings of the 9th ACM conference on Computer and communications security
An End-to-End Systems Approach to Elliptic Curve Cryptography
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
A digit-serial multiplier for finite field GF(2m)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient Algorithms and Architectures for Field Multiplication Using Gaussian Normal Bases
IEEE Transactions on Computers
A fast digit-serial systolic multiplier for finite field GF(2m)
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimum Digit Serial GF(2^m) Multipliers for Curve-Based Cryptography
IEEE Transactions on Computers
High-speed hardware implementations of Elliptic Curve Cryptography: A survey
Journal of Systems Architecture: the EUROMICRO Journal
Hardware acceleration of the Tate pairing on a genus 2 hyperelliptic curve
Journal of Systems Architecture: the EUROMICRO Journal
Multi-segment GF(2m) multiplication and its application to elliptic curve cryptography
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Low-complexity versatile finite field multiplier in normal basis
EURASIP Journal on Applied Signal Processing
Computers and Electrical Engineering
On efficient implementation of FPGA-based hyperelliptic curve cryptosystems
Computers and Electrical Engineering
Hardware architectures for the Tate pairing over GF(2m)
Computers and Electrical Engineering
On concurrent detection of errors in polynomial basis multiplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Versatile multiplier architectures in GF(2k) fields using the Montgomery multiplication algorithm
Integration, the VLSI Journal
Fast elliptic curve cryptography on FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Coprocessor for the Final Exponentiation of the ηTPairing in Characteristic Three
WAIFI '07 Proceedings of the 1st international workshop on Arithmetic of Finite Fields
Arithmetic Operators for Pairing-Based Cryptography
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Collision Search for Elliptic Curve Discrete Logarithm over GF(2m) with FPGA
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Digit-Serial Structures for the Shifted Polynomial Basis Multiplication over Binary Extension Fields
WAIFI '08 Proceedings of the 2nd international workshop on Arithmetic of Finite Fields
Pairing '08 Proceedings of the 2nd international conference on Pairing-Based Cryptography
FPGA implementations of elliptic curve cryptography and Tate pairing over a binary field
Journal of Systems Architecture: the EUROMICRO Journal
Elliptic Curve Cryptography on FPGA for Low-Power Applications
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Energy Efficient Elliptic Curve Processor
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
On parallelization of high-speed processors for elliptic curve cryptography
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
FPGA and ASIC implementations of the ηT pairing in characteristic three
Computers and Electrical Engineering
A cryptographic processor for arbitrary elliptic curves over GF(2m)
A cryptographic processor for arbitrary elliptic curves over GF(2m)
Multiplication over Fpm on FPGA: a survey
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
Hardware performance characterization of block cipher structures
CT-RSA'03 Proceedings of the 2003 RSA conference on The cryptographers' track
A flexible processor for the characteristic 3 ηT pairing
International Journal of High Performance Systems Architecture
Efficient finite field processor for GF(2163) and its implementation
International Journal of High Performance Systems Architecture
A new bit-serial multiplier over GF(pm) using irreducible trinomials
Computers & Mathematics with Applications
Scan-based attack against elliptic curve cryptosystems
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
On efficient implementation of accumulation in finite field over GF(2m) and its applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new digit-serial systolic mulitplier for high performance GF(2m) applications
HPCC'05 Proceedings of the First international conference on High Performance Computing and Communications
Hyperelliptic curve coprocessors on a FPGA
WISA'04 Proceedings of the 5th international conference on Information Security Applications
Complexity analysis of finite field digit serial multipliers on FPGAs
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
Scalable Gaussian Normal Basis Multipliers over GF(2m) Using Hankel Matrix-Vector Representation
Journal of Signal Processing Systems
Low power elliptic curve cryptography
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Low-power and high-speed design of a versatile bit-serial multiplier in finite fields GF(2m)
Integration, the VLSI Journal
Utilization of Pipeline Technique in AOP Based Multipliers with Parallel Inputs
Journal of Signal Processing Systems
| Hi-index | 0.03 |
Digit-serial architectures are best suited for systems requiringmoderate sample rate and where area and power consumption are critical. Thispaper presents a new approach for designing digit-serial/parallel finitefield multipliers. This approach combines both array-type and parallelmultiplication algorithms, where the digit-level array-type algorithmminimizes the latency for one multiplication operation and the parallelarchitecture inside of each digit cell reduces both the cycle-time as wellas the switching activities, hence power consumption. By appropriatelyconstraining the feasible primitive polynomials, the mod p(x)operation involved in finite field multiplication can be performed in a moreefficient way. As a result, the computation delay and energy consumption ofone finite field multiplication using the proposed digit-serial/parallelarchitectures are significantly less than of those obtained by folding theparallel semi-systolic multipliers. Furthermore, their energy-delay productsare reduced by a even larger percentage. Therefore, the proposeddigit-serial/parallel architectures are attractive for both low-energyand high-performance applications.