Hardware performance characterization of block cipher structures

Authors:
Lu Xiao;Howard M. Heys
Affiliations:
Electrical and Computer Engineering, Faculty of Engineering and Applied Science, Memorial University of Newfoundland, St. John's, NF, Canada;Electrical and Computer Engineering, Faculty of Engineering and Applied Science, Memorial University of Newfoundland, St. John's, NF, Canada
Venue:
CT-RSA'03 Proceedings of the 2003 RSA conference on The cryptographers' track
Year:
2003

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Abstract

Recently, there has been a lot of interest on cryptographic applications based on fields GF(pm), for pGF(pm) multipliers architectures, where p is odd. We present designs which trade area for performance based on the number of coefficients that the multiplier processes at one time. Families of irreducible polynomials are introduced to reduce the complexity of the modulo reduction operation and, thus, improved the efficiency of the multiplier. We, then, specialize to fields GF(3m) and provide the first cubing architecture presented in the literature. We synthesize our architectures for the special case of GF(397) on the XCV1000-8-FG1156 and XC2VP20-7-FF1156 FPGAs and provide area/performance numbers and comparisons to previous GF(3m) and GF(2m) implementations. Finally, we provide tables of irreducible polynomials over GF(3) of degree m with 2 ≤ m ≥ 255.