Hardware performance characterization of block cipher structures
CT-RSA'03 Proceedings of the 2003 RSA conference on The cryptographers' track
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient semisystolic architectures for finite-field arithmetic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents an efficient Reed-Solomon encoder based on standard basis. The key operation in Reed-Solomon encoding is the multiplication of a feedback term with several (possibly) known terms. We present an efficient structure to implement this operation. The hardware complexity of this encoder is identical to the well-known Berlekamp encoder. It however, offers two advantages over the Berlekamp encoder-a critical path independent of the order of Reed-Solomon code being implemented and the ability to encode without any need for basis conversion.