Introduction to finite fields and their applications
Introduction to finite fields and their applications
VLSI array processors
A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases
IEEE Transactions on Computers
Low-Energy Digit-Serial/Parallel Finite Field Multipliers
Journal of VLSI Signal Processing Systems - Special issue on application specific systems, architectures and processors
Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computers
Reed-Solomon Codes and Their Applications
Reed-Solomon Codes and Their Applications
Architecture For A Low Complexity Rate-Adaptive Reed-Solomon Encoder
IEEE Transactions on Computers
Efficient Finite Field Serial/Parallel Multiplication
ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
A Versatile and Scalable Digit-Serial/Parallel Multiplier Architecture for Finite Fields GF(2m)
ITCC '03 Proceedings of the International Conference on Information Technology: Computers and Communications
Parallel Multipliers Based on Special Irreducible Pentanomials
IEEE Transactions on Computers
A digit-serial multiplier for finite field GF(2m)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fast digit-serial systolic multiplier for finite field GF(2m)
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Bit-Parallel Finite Field Multipliers for Irreducible Trinomials
IEEE Transactions on Computers
Efficient standard basis Reed-Solomon encoder
ICASSP '96 Proceedings of the Acoustics, Speech, and Signal Processing, 1996. on Conference Proceedings., 1996 IEEE International Conference - Volume 06
On efficient implementation of accumulation in finite field over GF(2m) and its applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient semisystolic architectures for finite-field arithmetic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low complexity bit parallel architectures for polynomial basis multiplication over GF(2m)
IEEE Transactions on Computers
IEEE Transactions on Circuits and Systems for Video Technology
Complexity analysis of finite field digit serial multipliers on FPGAs
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
Integration, the VLSI Journal
Low-complexity multiplier for GF(2m) based on all-one polynomials
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low latency systolic montgomery multiplier for finite field GF(2m) based on pentanomials
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we present efficient algorithms for modular reduction to derive novel systolic and nonsystolic architectures for polynomial basis finite field multipliers over GF(2m) to be used in Reed-Solomon (RS) codec. Using the proposed algorithm for unit degree reduction and optimization of implementation of the logic functions in the processing elements (PEs), we have derived an efficient bit-parallel systolic design for finite field multiplier which involves nearly two-thirds of the area-complexity of the existing design having the same time-complexity. The proposed modular reduction algorithms are also used to derive efficient non-systolic serial/parallel designs of field multipliers over GF(28) with different digit-sizes, where the critical path and the hardware-complexity are further reduced by optimizing the implementation of modular reduction operations and finite field accumulations. The proposed bit-serial design involves nearly 55% of the minimum of area, and half the minimum of area-time complexity of the existing bit-serial designs. Similarly, the proposed digit-serial/parallel designs involve significantly less area, and less area-time complexities compared with the existing designs of the same digit-size. By parallel modular reduction through multiple degrees followed by appropriate logic-level sub-expression sharing; a hardware-efficient regular and modular form of a balanced-tree bit-parallel non-systolic multiplier is also derived. The proposed bit-parallel non-systolic pipelined design involves less than 65% of the area and nearly two-thirds of the area-time complexity of the existing bit-parallel design for a RS codec, while the non-pipelined form offers nearly 25% saving of area with less time-complexity.