Structure of parallel multipliers for a class of fields GF(2m)
Information and Computation
Mastrovito Multiplier for All Trinomials
IEEE Transactions on Computers
IEEE Transactions on Computers
INDOCRYPT '01 Proceedings of the Second International Conference on Cryptology in India: Progress in Cryptology
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Low-Complexity Bit-Parallel Systolic Montgomery Multipliers for Special Classes of GF(2^m)
IEEE Transactions on Computers
A digit-serial multiplier for finite field GF(2m)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computers
Relationship between GF(2^m) Montgomery and Shifted Polynomial Basis Multiplication Algorithms
IEEE Transactions on Computers
LFSR multipliers over GF(2m) defined by all-one polynomial
Integration, the VLSI Journal
Bit-Parallel Polynomial Basis Multiplier for New Classes of Finite Fields
IEEE Transactions on Computers
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Concurrent Error Detection and Correction in Gaussian Normal Basis Multiplier over GF(2^m)
IEEE Transactions on Computers
Ringed bit-parallel systolic multipliers over a class of fields GF(2m)
Integration, the VLSI Journal
Low complexity digit serial systolic montgomery multipliers for special class of GF(2m)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ISPA '10 Proceedings of the International Symposium on Parallel and Distributed Processing with Applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents an area-time-efficient systolic structure for multiplication over GF(2m) based on irreducible all-one polynomial (AOP). We have used a novel cut-set retiming to reduce the duration of the critical-path to one XOR gate delay. It is further shown that the systolic structure can be decomposed into two or more parallel systolic branches, where the pair of parallel systolic branches has the same input operand, and they can share the same input operand registers. From the application-specific integrated circuit and field-programmable gate array synthesis results we find that the proposed design provides significantly less area-delay and power-delay complexities over the best of the existing designs.