A digit-serial multiplier for finite field GF(2m)

Authors:
Chang Hoon Kim;Chun Pyo Hong;Soonhak Kwon
Affiliations:
Department of Computer and Information Engineering, Daegu University, Kyungsan 712-714, Korea;Department of Computer and Communication Engineering, Daegu University, Kyungsan 712-714, Korea;Department of Mathematics and Institute of Basic Science, Sungkyunkwan University, Suwon 440-746, Korea
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2005

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Abstract

In this paper, an efficient digit-serial systolic array is proposed for multiplication in finite field GF(2m) using the standard basis representation. From the least significant bit first multiplication algorithm, we obtain a new dependence graph and design an efficient digit-serial systolic multiplier. If input data come in continuously, the proposed array can produce multiplication results at a rate of one every ⌈m/L⌉ clock cycles, where L is the selected digit size. Analysis shows that the computational delay time of the proposed architecture is significantly less than the previously proposed digit-serial systolic multiplier. Furthermore, since the new architecture has the features of regularity, modularity, and unidirectional data flow, it is well suited to VLSI implementation.