Architectural support for fast symmetric-key cryptography
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Performance-Scalable Array Architectures for Modular Multiplication
Journal of VLSI Signal Processing Systems
Inversion/Division Systolic Architecture for Public-Key Cryptosystems in GF(2m)
ISC '02 Proceedings of the 5th International Conference on Information Security
High-Radix Design of a Scalable Modular Multiplier
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Hardware architectures for public key cryptography
Integration, the VLSI Journal
Systolic architectures for inversion/division using AB2 circuits in GF(2m)
Integration, the VLSI Journal
A digit-serial multiplier for finite field GF(2m)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A New Systolic Architecture for Modular Division
IEEE Transactions on Computers
Montgomery exponent architecture based on programmable cellular automata
Mathematics and Computers in Simulation
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The authors present two systolic architectures to speed up the computation of modular multiplication in RSA cryptosystems. In the double-layer architecture, the main operation of Montgomery's algorithm is partitioned into two parallel operations after using the precomputation of the quotient bit. In the non-interlaced architecture, we eliminate the one-clock-cycle gap between iterations by pairing off the double-layer architecture. We compare our architectures with some previously proposed Montgomery-based systolic architectures, on the basis of both modular multiplication and modular exponentiation. The comparisons indicate that our architectures offer the highest speed, lower hardware complexity, and lower power consumption.