Security for computer networks: and introduction to data security in teleprocessing and electronic funds transfer (2nd ed.)
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
ESA/390 integrated cryptographic facility: an overview
IBM Systems Journal - Special issue on cryptology
Web server workload characterization: the search for invariants
Proceedings of the 1996 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Exceeding the dataflow limit via value prediction
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
An improved Montgomery's algorithm for high-speed RSA public-key cryptosystem
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Two systolic architectures for modular multiplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Radix-4 modular multiplication and exponentiation algorithms for the RSA public-key cryptosystem
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Bit Permutation Instructions for Accelerating Software Cryptography
ASAP '00 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Montgomery Modular Exponentiation on Reconfigurable Hardware
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
S/390 CMOS cryptographic coprocessor architecture: overview and design considerations
IBM Journal of Research and Development
Architectural support for copy and tamper resistant software
ACM SIGPLAN Notices
Architectural support for copy and tamper resistant software
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
CryptoManiac: a fast flexible architecture for secure communication
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Application specific architectures: a recipe for fast, flexible and power efficient designs
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
System design methodologies for a wireless security processing platform
Proceedings of the 39th annual Design Automation Conference
Securing wireless data: system architecture challenges
Proceedings of the 15th international symposium on System Synthesis
Analyzing the energy consumption of security protocols
Proceedings of the 2003 international symposium on Low power electronics and design
Architectural techniques for accelerating subword permutations with repetitions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Fast Secure Processor for Inhibiting Software Piracy and Tampering
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Emerging challenges in designing secure mobile appliances
Ambient intelligence
Security as a new dimension in embedded system design
Proceedings of the 41st annual Design Automation Conference
Security in embedded systems: Design challenges
ACM Transactions on Embedded Computing Systems (TECS)
Securing Mobile Appliances: New Challenges for the System Designer
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Improving Memory Encryption Performance in Secure Processors
IEEE Transactions on Computers
A Study of the Energy Consumption Characteristics of Cryptographic Algorithms and Security Protocols
IEEE Transactions on Mobile Computing
Proceedings of the 43rd annual Design Automation Conference
NPCryptBench: a cryptographic benchmark suite for network processors
MEDEA '05 Proceedings of the 2005 workshop on MEmory performance: DEaling with Applications , systems and architecture
ASIP architecture exploration for efficient IPSec encryption: A case study
ACM Transactions on Embedded Computing Systems (TECS) - SPECIAL ISSUE SCOPES 2005
Hybrid architectures for efficient and secure face authentication in embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Configuration and extension of embedded processors to optimize IPSec protocol execution
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploring software partitions for fast security processing on a multiprocessor mobile SoC
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Implementation of secure applications in self-reconfigurable systems
Microprocessors & Microsystems
Accelerated AES implementations via generalized instruction set extensions
Journal of Computer Security - The Third IEEE International Symposium on Security in Networks and Distributed Systems
Efficient software architecture for IPSec acceleration using a programmable security processor
Proceedings of the conference on Design, automation and test in Europe
Light-Weight Instruction Set Extensions for Bit-Sliced Cryptography
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
Fast Bit Gather, Bit Scatter and Bit Permutation Instructions for Commodity Microprocessors
Journal of Signal Processing Systems
Parallelization of prime number generation using message passing interface
WSEAS Transactions on Computers
Accurate modeling for predicting cryptography overheads on wireless sensor nodes
ICACT'09 Proceedings of the 11th international conference on Advanced Communication Technology - Volume 2
Boosting AES performance on a tiny processor core
CT-RSA'08 Proceedings of the 2008 The Cryptopgraphers' Track at the RSA conference on Topics in cryptology
Enhancing the performance of symmetric-key cryptography via instruction set extensions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Workload characterization of cryptography algorithms for hardware acceleration
Proceedings of the 2nd ACM/SPEC International Conference on Performance engineering
Parallelization of prime number generation using message passing interface
CIMMACS'07 Proceedings of the 6th WSEAS international conference on Computational intelligence, man-machine systems and cybernetics
Instruction set extensions for efficient AES implementation on 32-bit processors
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Data protection based on physical separation: concepts and application scenarios
ICCSA'05 Proceedings of the 2005 international conference on Computational Science and Its Applications - Volume Part IV
Hardware-software co-design of AES on FPGA
Proceedings of the International Conference on Advances in Computing, Communications and Informatics
Editorial: Recent developments in high performance computing and security: An editorial
Future Generation Computer Systems
RFIDSec'12 Proceedings of the 8th international conference on Radio Frequency Identification: security and privacy issues
Hi-index | 0.00 |
The emergence of the Internet as a trusted medium for commerce and communication has made cryptography an essential component of modern information systems. Cryptography provides the mechanisms necessary to implement accountability, accuracy, and confidentiality in communication. As demands for secure communication bandwidth grow, efficient cryptographic processing will become increasingly vital to good system performance.In this paper, we explore techniques to improve the performance of symmetric key cipher algorithms. Eight popular strong encryption algorithms are examined in detail. Analysis reveals the algorithms are computationally complex and contain little parallelism. Overall throughput on a high-end microprocessor is quite poor, a 600 Mhz processor is incapable of saturating a T3 communication line with 3DES (triple DES) encrypted data.We introduce new instructions that improve the efficiency of the analyzed algorithms. Our approach adds instruction set support for fast substitutions, general permutations, rotates, and modular arithmetic. Performance analysis of the optimized ciphers shows an overall speedup of 59% over a baseline machine with rotate instructions and 74% speedup over a baseline without rotates. Even higher speedups are demonstrated with optimized substitutions (SBOXes) and additional functional unit resources. Our analyses of the original and optimized algorithms suggest future directions for the design of high-performance programmable cryptographic processors.