ASIP architecture exploration for efficient IPSec encryption: A case study

Authors:
Hanno Scharwaechter;David Kammler;Andreas Wieferink;Manuel Hohenauer;Kingshuk Karuri;Jianjiang Ceng;Rainer Leupers;Gerd Ascheid;Heinrich Meyr
Affiliations:
RWTH Aachen University, Aachen, Germany;RWTH Aachen University, Aachen, Germany;RWTH Aachen University, Aachen, Germany;RWTH Aachen University, Aachen, Germany;RWTH Aachen University, Aachen, Germany;RWTH Aachen University, Aachen, Germany;RWTH Aachen University, Aachen, Germany;RWTH Aachen University, Aachen, Germany;RWTH Aachen University, Aachen, Germany
Venue:
ACM Transactions on Embedded Computing Systems (TECS) - SPECIAL ISSUE SCOPES 2005
Year:
2007

Citing 15
Cited 4

EXPRESSION: a language for architecture exploration through compiler/simulator retargetability

DATE '99 Proceedings of the conference on Design, automation and test in Europe
Fast implementations of secret-key block ciphers using mixed inner- and outer-round pipelining

FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Network processors: a perspective on market requirements, processor architectures and embedded S/W tools

Proceedings of the conference on Design, automation and test in Europe
Architectural support for fast symmetric-key cryptography

ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
A universal technique for fast and flexible instruction-set architecture simulation

Proceedings of the 39th annual Design Automation Conference
System Design with SystemC

System Design with SystemC
Architecture Exploration for Embedded Processors with Lisa

Architecture Exploration for Embedded Processors with Lisa
Describing instruction set processors using nML

EDTC '95 Proceedings of the 1995 European conference on Design and Test
A Bit-Serial Implementation of the International Data Encryption Algorithm IDEA

FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Processor Modeling for Hardware Software Codesign

VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models

Proceedings of the conference on Design, automation and test in Europe - Volume 2
A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platforms

Proceedings of the conference on Design, automation and test in Europe - Volume 2
RTL Processor Synthesis for Architecture Exploration and Implementation

Proceedings of the conference on Design, automation and test in Europe - Volume 3
Introduction of local memory elements in instruction set extensions

Proceedings of the 41st annual Design Automation Conference
Implementing IPv6 for Windows NT

WINSYM'98 Proceedings of the 2nd conference on USENIX Windows NT Symposium - Volume 2

Fine-grained application source code profiling for ASIP design

Proceedings of the 42nd annual Design Automation Conference
A code-generator generator for multi-output instructions

CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Two versions of architectures for dynamic implied addressing mode

Journal of Systems Architecture: the EUROMICRO Journal
Implementing dynamic implied addressing mode for multi-output instructions

CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Application-Specific Instruction-Set Processors (ASIPs) are becoming increasingly popular in the world of customized, application-driven System-on-Chip (SoC) designs. Efficient ASIP design requires an iterative architecture exploration loop---gradual refinement of the processor architecture starting from an initial template. To accomplish this task, design automation tools are used to detect bottlenecks in embedded applications, to implement application-specific processor instructions, and to automatically generate the required software tools (such as instruction-set simulator, C-compiler, assembler, and profiler), as well as to synthesize the hardware. This paper describes an architecture exploration loop for an ASIP coprocessor that implements common encryption functionality used in symmetric block cipher algorithms for internet protocol security (IPSec). The coprocessor is accessed via shared memory and, as a consequence, our approach is easily adaptable to arbitrary main processor architectures. This paper presents the extended version of our case study that has been already published on the SCOPES conference in 2004. In both papers, a MIPS architecture is used as the main processor and Blowfish as encryption algorithm.