Industrial experience using rule-driven retargetable code generation for multimedia applications
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Time-constrained code compaction for DSP's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Code generation algorithms for digital signal processors
Code generation algorithms for digital signal processors
Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator
DAC '98 Proceedings of the 35th annual Design Automation Conference
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Retargetable compiler technology for embedded systems: tools and applications
Retargetable compiler technology for embedded systems: tools and applications
A universal technique for fast and flexible instruction-set architecture simulation
Proceedings of the 39th annual Design Automation Conference
Code Optimization Techniques for Embedded Processors: Methods, Algorithms, and Tools
Code Optimization Techniques for Embedded Processors: Methods, Algorithms, and Tools
A Retargetable C Compiler: Design and Implementation
A Retargetable C Compiler: Design and Implementation
Architecture Exploration for Embedded Processors with Lisa
Architecture Exploration for Embedded Processors with Lisa
Guest Editors' Introduction: Application-Specific Microprocessors
IEEE Design & Test
Instruction Scheduler Generation for Retargetable Compilation
IEEE Design & Test
Describing instruction set processors using nML
EDTC '95 Proceedings of the 1995 European conference on Design and Test
RTL Processor Synthesis for Architecture Exploration and Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 3
C Compiler Retargeting Based on Instruction Semantics Models
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting
Journal of VLSI Signal Processing Systems
Retargetable code optimization with SIMD instructions
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
ASIP architecture exploration for efficient IPSec encryption: A case study
ACM Transactions on Embedded Computing Systems (TECS) - SPECIAL ISSUE SCOPES 2005
Retargetable code optimization for predicated execution
Proceedings of the conference on Design, automation and test in Europe
Processor Description Languages
Processor Description Languages
A SIMD optimization framework for retargetable compilers
ACM Transactions on Architecture and Code Optimization (TACO)
Compiler backend generation for application specific instruction set processors
APLAS'11 Proceedings of the 9th Asian conference on Programming Languages and Systems
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Retargetable C compilers are key tools for efficient architecture exploration for embedded processors. In this paper we describe a novel approach to retargetable compilation based on LISA, an industrial processor modeling language for efficient ASIP design. In order to circumvent the well-known trade-off between flexibility and code quality in retargetable compilation, we propose a user-guided, semi-automatic methodology that in turn builds on a powerful existing C compiler design platform. Our approach allows to include generated C compilers into the ASIP architecture exploration loop at an early stage, thereby allowing for a more efficient design process and avoiding application/architecture mismatches. We present the corresponding methodology and tool suite and provide experimental data for two real-life embedded processors that prove the feasibility of the approach.